ATMEL AT 32 AP 7002 Service Manual
www.DataSheet4U.com
Features
• High Performance, Low Power AVR
– 210 DMIPS throughput at 150 MHz
– 16 KB instruction cache and 16 KB data caches
– Memory Management Unit enabling use of operating systems
– Single-cycle RISC instruction set including SIMD and DSP instructions
– Java Hardware Acceleration
• Multimedia Co-Processor
– Vector Multiplication Unit for video acceleration through color-space conversion
(YUV<->RGB), image scaling and filtering, quarter pixel motion compensation
• Multi-hierarchy bus system
– High-performance data transfers on separate buses for increased performance
• Data Memories
– 32KBytes SRAM
• External Memory Interface
– SDRAM, DataFlash™, SRAM, Multi Media Card (MMC), Secure Digital (SD),
– Compact Flash, Smart Media, NAND Flash
• Direct Memory Access Controller
– External Memory access without CPU intervention
• Interrupt Controller
– Individually maskable Interrupts
– Each interrupt request has a programmable priority and autovector address
• System Functions
– Power and Clock Manager
– Crystal Oscillator with Phase-Lock-Loop (PLL)
– Watchdog Timer
– Real-time Clock
• 6 Multifunction timer/counters
– Three external clock inputs, I/O pins, PWM, capture and various counting
capabilities
• 4 Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– 115.2 kbps IrDA Modulation and Demodulation
– Hardware and software handshaking
• 3 Synchronous Serial Protocol controllers
– Supports I2S, SPI and generic frame-based protocols
• Two-Wir e Inte rfac e
– Sequential Read/Write Operations, Philips’ I2C© compatible
• Liquid Crystal Display (LCD) interface
– Supports TFT displays
– Configurable pixel resolution supporting QCIF/QVGA/VGA/SVGA configurations.
• Image Sensor Interface
– 12-bit Data Interface for CMOS cameras
• Universal Serial Bus (USB) 2.0 High Speed (480 Mbps) Device
– On-chip Transceivers with physical interface
• 16-bit stereo audio DAC
– Sample rates up to 50 kHz
• On-Chip Debug System
– Nexus Class 3
– Full speed, non-intrusive data and program trace
– Runtime control and JTAG interface
• Package/Pins
– AT32AP7002: 196-ball CTBGA
• Power supplies
– 1.65V to1.95V VDDCORE
– 3.0V to 3.6V VDDIO
®
32 32-Bit Microcontroller
AVR®32 32-bit
Microcontroller
AT32AP7002
Preliminary
Summary
32054AS-AVR32-02/07
1. Part Description
The AT32AP7002 is a complete System-on-chip application processor with an AVR32 RISC
processor achieving 210 DMIPS running 150 MHz. AVR32 is a high-performance 32-bit RISC
microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high application performance.
AT32AP7002 implements a Memory Management Unit (MMU) and a flexible interrupt controller
supporting modern operating systems and real-time operating systems. The processor also
includes a rich set of DSP and SIMD instructions, specially designed for multimedia and telecom
applications.
AT32AP7002 incorporates SRAM memories on-chip for fast and secure access. For applications requiring additional memory, external 16-bit SRAM is accessible. Additionally, an SDRAM
controller provides off-chip volatile memory access as well as controllers for all industry standard
off-chip non-volatile memories, like Compact Flash, Multi Media Card (MMC), Secure Digital
(SD)-card, SmartCard, NAND Flash and Atmel DataFlash™.
The Direct Memory Access controller for all the serial peripherals enables data transfer between
memories without processor intervention. This reduces the processor overhead when transferring continuous and large data streams between modules in the MCU.
The Timer/Counters includes three identical 16-bit timer/counter channels. Each channel can be
independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width
modulation.
AT32AP7002
AT32AP7002 also features an onboard LCD Controller, supporting single and double scan
monochrome and color passive STN LCD modules and single scan active TFT LCD modules.
On monochrome STN displays, up to 16 gray shades are supported using a time-based dithering algorithm and Frame Rate Control (FRC) method. This method is also used in color STN
displays to generate up to 4096 colors.
The LCD Controller is programmable for supporting resolutions up to 2048 x 2048 with a pixel
depth from 1 to 24 bits per pixel.
A pixel co-processor provides color space conversions for images and video, in addition to a
wide variety of hardware filter support
The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC modules
provides on-chip solutions for network-connected devices.
Synchronous Serial Controllers provide easy access to serial communication protocols, audio
standards like AC'97, I2S, I2C© and various SPI modes. The modules support frame-based protocols, like VoIP SIP protocols.
The Java hardware acceleration implementation in AVR32 allows for a very high-speed Java
byte-code execution. AVR32 implements Java instructions in hardware, reusing the existing
RISC data path, which allows for a near-zero hardware overhead and cost with a very high
performance.
The Image Sensor Interface supports cameras with up to 12-bit data buses and connects
directly to the LCD interface through a separate bus.
32054AS-AVR32-02/07
PS2 connectivity is provided for standard input devices like mice and keyboards.
2
AT32AP7002
AT32AP7002 integrates a class 3 Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive
real-time trace, full-speed read/write memory access in addition to basic runtime control.
The C-compiler is closely linked to the architecture and is able to utilize code optimization features, both for size and speed.
32054AS-AVR32-02/07
3
2. Blockdiagram
Figure 2-1. Blockdiagram
TRST_N
TCK
TDO
TDI
TMS
EVTI_N
D+
D-
DATA[11..0]
HSYNC
VSYNC
PCLK
PA
PB
PC
PD
PE
XIN32
XOUT32
XIN0
XOUT0
XIN1
XOUT1
PLL0
PLL1
OSCEN_N
Parallel Input/Output Controllers
RESET_N
A
D
D
A
A
D
T
D
T
A
C
CMD
DATA[7..0]
C
S
S
S
S
S
32 KHz
OSC
OSC0
OSC1
PLL0
PLL1
G
K
L
C
INTERFACE
MCKO
MDO[5..0]
MSEO[1..0]
EVTO_N
INTERFACE
SENSOR
INTERFACE
INTRAM0
INTRAM1
0
T
A
1
A
T
N
0
A
A
N
1
L
K
K
L
D
I
C
N
Y
O
D
3
[
]
0
.
.
JTAG
USB
DMA
IMAGE
PB
DMA CONTROLLER
AUDIO BITSTREAM
DAC
MULTIMEDIA CARD
INTERFACE
AC97 CONTROLLER
POWER
MANAGER
CLOCK
GENERATOR
CLOCK
CONTROLLER
SLEEP
CONTROLLER
RESET
CONTROLLER
NEXUS
CLASS 3
PBB
S
M
M
S
HSB
HSB-PB
BRIDGE
B
OCD
MEMORY MANAGEMENT UNIT
INSTR
CACHE
M
M
HIGH SPEED
BUS MATRIX
S
SMM
CONFIGURATION REGISTERS BUS
S
HSB
HSB-PB
BRIDGE A
PB
PBA
DMA
DMA
DMA
AP CPU
DATA
CACHE
HSB-HSB BRIDGE
PERIPHERAL
CONTROLLER
PDC
PERIPHERAL
PDC
INTERFACE 0/1
SYNCHRONOUS
PDC
CONTROLLER 0/1/2
TWO-WIRE
INTERFACE
PS2 INTERFACE
REAL TIME
COUNTER
WATCHDOG
M
M
DMA
USART0
USART1
USART2
USART3
SERIAL
SERIAL
TIMER
AT32AP7002
PIXEL COPROCESSOR
VSYNC,
HSYNC,
DATA[22..0],
NANDOE,
NANDWE,
SDCKE,
NCS[3,1,0],
ADDR[22..0]
NCS[5,4,2]
CFRNW,
CFCE1,
CONTROLLER & ECC)
CFCE2,
ADDR[23..25]
DATA[31..16]
RXD
TXD
CLK
RTS, CTS
SCK
MISO, MOSI
NPCS0
NPCS[3..1]
TX_DATA
RX_DATA
SCL
SDA
CLOCK[1..0]
DATA[1..0]
PWR,
PCLK,
MODE,
DVAL,
CC,
GPL[7..0]
RAS,
CAS,
SDWE,
SDCK,
NWE3,
NWE1,
NWE0,
NRD,
NWAIT
SDCS,
DATA[15..0]
PA
PB
PC
PD
PE
Parallel Input/Output Controllers
LCD
CONTRO
LLER
S
M
DMA
S
(SDRAM & STATIC MEMORY
EXTERNAL BUS INTERFACE
TX_CLOCK, TX_FRAME_SYNC
RX_CLOCK, RX_FRAME_SYNC
32054AS–AVR32–02/07
A
B
CLK[2..0]
X
E
T
K
P
NMI_N
.
.
0
]
[
2
2
[
0
]
.
.
T
I
N
S
[
7
TIMER/COUNTER 0/1
.
0
]
.
[
7
.
0
.
]
EXTERNAL
INTERRUPT
CONTROLLER
INTERRUPT
CONTROLLER
PULSE WIDTH
MODULATION
CONTROLLER
PWM0
PWM1
PWM2
PWM3
4
2.1 Processor and architecture
2.1.1 AVR32AP CPU
•
32-bit load/store AVR32B RISC architecture.
– Up to 15 general-purpose 32-bit registers.
– 32-bit Stack Pointer, Program Counter and Link Register reside in register file.
– Fully orthogonal instruction set.
– Privileged and unprivileged modes enabling efficient and secure Operating Systems.
– Innovative instruction set together with variable instruction length ensuring industry leading
code density.
– DSP extention with saturating arithmetic, and a wide variety of multiply instructions.
– SIMD extention for media applications.
• 7 stage pipeline allows one instruction per clock cycle for most instructions.
– Java Hardware Acceleration.
– Byte, half-word, word and double word memory access.
– Unaligned memory access.
– Shadowed interrupt context for INT3 and multiple interrupt priority levels.
– Dynamic branch prediction and return address stack for fast change-of-flow.
– Coprocessor interface.
• Full MMU allows for operating systems with memory protection.
• 16Kbyte Instruction and 16Kbyte data caches.
– Virtually indexed, physically tagged.
– 4-way associative.
– Write-through or write-back.
• Nexus Class 3 On-Chip Debug system.
– Low-cost NanoTrace supported.
AT32AP7002
2.1.2 Pixel Coprocessor (PiCo)
Coprocessor coupled to the AVR32 CPU Core through the TCB Bus.
•
• Three parallel Vector Multiplication Units (VMU) where each unit can:
– Multiply three pixel components with three coefficients.
– Add the products from the multiplications together.
– Accumulate the result or add an offset to the sum of the products.
• Can be used for accelerating:
– Image Color Space Conversion.
•Configurable Conversion Coefficients.
• Supports packed and planar input and output formats.
• Supports subsampled input color spaces (i.e 4:2:2, 4:2:0).
– Image filtering/scaling.
• Configurable Filter Coefficients.
• Throughput of one sample per cycle for a 9-tap FIR filter.
• Can use the built-in accumulator to extend the FIR filter to more than 9-taps.
• Can be used for bilinear/bicubic interpolations.
– MPEG-4/H.264 Quarter Pixel Motion Compensation.
• Flexible input Pixel Selector.
– Can operate on numerous different image storage formats.
• Flexible Output Pixel Inserter.
– Scales and saturates the results back to 8-bit pixel values.
32054AS–AVR32–02/07
5
– Supports packed and planar output formats.
• Configurable coefficients with flexible fixed-point representation.
2.1.3 Debug and Test system
IEEE1149.1 compliant JTAG and boundary scan
•
• Direct memory access and programming capabilities through JTAG interface
• Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 3
• Auxiliary port for high-speed trace information
• Hardware support for 6 Program and 2 data breakpoints
• Unlimited number of software breakpoints supported
• Advanced Program, Data, Ownership, and Watchpoint trace supported
2.1.4 DMA controller
2 HSB Master Interfaces
•
• 3 Channels
• Software and Hardware Handshaking Interfaces
– 11 Hardware Handshaking Interfaces
• Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer
• Single-block DMA Transfer
• Multi-block DMA Transfer
– Linked Lists
– Auto-Reloading
– Contiguous Blocks
• DMA Controller is Always the Flow Controller
• Additional Features
– Scatter and Gather Operations
– Channel Locking
Bus Locking
–
– FIFO Mode
– Pseudo Fly-by Operation
AT32AP7002
2.1.5 Peripheral DMA Controller
Transfers from/to peripheral to/from any memory space without intervention of the processor.
•
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• Eighteen channels
– Two for each USART
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
2.1.6 Bus system
HSB bus matrix with 10 Masters and 8 Slaves handled
•
– Handles Requests from the CPU Icache, CPU Dcache, HSB bridge, HISI, USB 2.0 Controller,
LCD Controller, DMA Controller 0, DMA Controller 1, and to internal SRAM 0, internal SRAM 1,
PB A, PB B, EBI and, USB.
32054AS–AVR32–02/07
6
AT32AP7002
– Round-Robin Arbitration (three modes supported: no default master, last accessed default
master, fixed default master)
– Burst Breaking with Slot Cycle Limit
– One Address Decoder Provided per Master
• 2 Peripheral buses allowing each bus to run on different bus speeds.
– PB A intended to run on low clock speeds, with peripherals connected to the PDC.
– PB B intended to run on higher clock speeds, with peripherals connected to the DMAC.
• HSB-HSB Bridge providing a low-speed HSB bus running at the same speed as PBA
– Allows PDC transfers between a low-speed PB bus and a bus matrix of higher clock speeds
An overview of the bus system is given in Figure 2-1 on page 4. All modules connected to the
same bus use the same clock, but the clock to each module can be individually shut off by the
Power Manager. The figure identifies the number of master and slave interfaces of each module
connected to the HSB bus, and which DMA controller is connected to which peripheral.
32054AS–AVR32–02/07
7
2.2 Package and PinoutAVR32AP7002
Figure 2-2. 196 CTBGA Pinout
TOP VIEW BOTTOM VIEW
Ball A1
1413121110987654321 1413121110 9 8 7 6 5 4 3 2 1
AT32AP7002
A
B
C
D
E
F
G
H
J
K
L
M
N
P
AVR32
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Table 2-1. CTBGA196 Package Pinout A1..T8
12345678
PX49 PX48 PX47 AVDDPLL PC28 PC23 PC20 PB22
A
PX50 GND VDDIO PLL0 PLL1 XIN32 PC22 PB23
B
PX51 PD01 PX05 GND AGNDPLL XOUT32 PC29 PC21
C
PX32 PD00 VDDIO PX02 XIN0 XOUT0 AGNDOSC PC30
D
PX33 PX00 PX04 GND PD07 AVDDOSC OSCEN_N PC31
E
PX01 PX03 VDDCORE PD04 PD09 TDI RESET_N VDDCORE
F
PD05 PD08 PD06 TDO PA04 PA02 PA08 PX22
G
TMS TRST_N TCK EVTI_N PB24 PA10 PA14 PX38
H
PA 01 PA0 3 PA 0 0 V D D IO G ND PA 0 9 PA 1 8 G N D
J
PA 05 PA1 1 PA 1 2 PA 1 6 G ND G N D PA 2 6 WA K E _N
K
PB25 PA21 PA19 GND VDDIO VDDIO PA25 PA29
L
PA13 PA22 PA23 PD17 AVDDUSB VDDCORE VBG PA30
M
PA15 PA20 PD12 PD15 PD16 AGNDUSB FSDP HSDP
N
PA17 PA24 PD13 PD14 XIN1 XOUT1 FSDM HSDM
P
32054AS–AVR32–02/07
8
AT32AP7002
Table 2-2. CTBGA196 Package Pinout A9..T16
9 1011121314
PB18 PB16 PB11 PB08 PB05 PB04
A
PB21 PB17 PB12 PB09 PB06 PB03
B
PA06 PB19 PB14 PB10 PB07 PB02
C
VDDIO PB20 PB15 PB13 GND PB01
D
PA07 GND PB00 PX44 VDDIO PX45
E
PX42 GND GND PX43 PX46 PX40
F
PX30 PX25 PX31 VDDIO VDDCORE PX39
G
PA28 PX20 PX28 PX29 VDDCORE PX26
H
PB27 PX37 PX23 PX27 PX21 PX24
J
PB28 PX15 PX36 PX19 PX34 PX18
K
PX41 GND PX07 VDDIO GND PX35
L
PX53 PX06 PX11 PX12 PX17 PX14
M
PB26 VDDIO PX09 PB29 PX16 PX13
N
PA27 PA31 PX52 PX08 PX10 PB30
P
32054AS–AVR32–02/07
9
AT32AP7002
3. Signals Description
The following table gives details on the signal name classified by peripheral. The pinout multiplexing of these signals is given in the Peripheral Muxing table in the Peripherals chapter.
Table 3-1. Signal Description List
Active
Signal Name Function Type
Power
AVDDPLL PLL Power Supply Power 1.65 to 1.95 V
AVDDUSB USB Power Supply Power 1.65 to 1.95 V
AVDDOSC Oscillator Power Supply Power 1.65 to 1.95 V
VDDCORE Core Power Supply Power 1.65 to 1.95 V
VDDIO I/O Power Supply Power 3.0 to 3.6V
AGNDPLL PLL Ground Ground
AGNDUSB USB Ground Ground
Level Comments
AGNDOSC Oscillator Ground Ground
GND Ground Ground
Clocks, Oscillators, and PLL’s
XIN0, XIN1, XIN32 Crystal 0, 1, 32 Input Analog
XOUT0, XOUT1,
XOUT32
PLL0, PLL1 PLL 0,1 Filter Pin Analog
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
TRST_N Test Reset Input Low
MCKO Trace Data Output Clock Output
Crystal 0, 1, 32 Output Analog
JTAG
Auxiliary Port - AUX
MDO0 - MDO5 Trace Data Output Output
MSEO0 - MSEO1 Trace Frame Control Output
EVTI_N Event In Input Low
32054AS-AVR32-02/07
10
Table 3-1. Signal Description List
Active
Signal Name Function Type
EVTO_N Event Out Output Low
Power Manager - PM
GCLK0 - GCLK4 Generic Clock Pins Output
OSCEN_N Oscillator Enable Input Low
RESET_N Reset Pin Input Low
WAKE_N Wake Pin Input Low
External Interrupt Module - EIM
EXTINT0 - EXTINT3 External Interrupt Pins Input
NMI_N Non-Maskable Interrupt Pin Input Low
AC97 Controller - AC97C
Level Comments
AT32AP7002
SCLK AC97 Clock Signal Input
SDI AC97 Receive Signal Output
SDO AC97 Transmit Signal Output
SYNC AC97 Frame Synchronization Signal Input
DAC - DAC
DATA0 - DATA1 D/A Data Out Output
DATAN0 - DATAN1 D/A Inverted Data Out Output
External Bus Interface - EBI
ADDR0 - ADDR25 Address Bus Output
CAS Column Signal Output Low
CFCE1 Compact Flash 1 Chip Enable Output Low
CFCE2 Compact Flash 2 Chip Enable Output Low
CFRNW Compact Flash Read Not Write Output
DATA0 - DATA31 Data Bus I/O
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
NCS0 - NCS5 Chip Select Output Low
NRD Read Signal Output Low
32054AS-AVR32-02/07
11
Table 3-1. Signal Description List
Active
Signal Name Function Type
NWAIT External Wait Signal Input Low
NWE0 Write Enable 0 Output Low
NWE1 Write Enable 1 Output Low
NWE3 Write Enable 3 Output Low
RAS Row Signal Output Low
SDA10 SDRAM Address 10 Line Output
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output
SDCS SDRAM Chip Select Output Low
SDWE SDRAM Write Enable Output Low
Level Comments
AT32AP7002
Image Sensor Interface - ISI
DATA0 - DATA11 Image Sensor Data Input
HSYNC Horizontal Synchronization Input
PCLK Image Sensor Data Clock Input
VSYNC Vertical Synchronization Input
Mulitmedia Card Interface - MMCI
CLK Multimedia Card Clock Output
CMD0 - CMD1 Multimedia Card Command I/O
DATA0 - DATA7 Multimedia Card Data I/O
Parallel Input/Output 2 - PIOA, PIOB, PIOC, PIOD, PIOE
PA0 - PA31 Parallel I/O Controller PIOA I/O
PB0 - PB30 Parallel I/O Controller PIOB I/O
PC0 - PC31 Parallel I/O Controller PIOC I/O
PD0 - PD17 Parallel I/O Controller PIOD I/O
PE0 - PE26 Parallel I/O Controller PIOE I/O
PS2 Interface - PSIF
CLOCK0 - CLOCK1 PS2 Clock Input
DATA0 - DATA1 PS2 Data I/O
32054AS-AVR32-02/07
12
Table 3-1. Signal Description List
Active
Signal Name Function Type
Serial Peripheral Interface - SPI0, SPI1
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
NPCS0 - NPCS3 SPI Peripheral Chip Select I/O Low
SCK Clock Output
Synchronous Serial Controller - SSC0, SSC1, SSC2
RX_CLOCK SSC Receive Clock I/O
RX_DATA SSC Receive Data Input
RX_FRAME_SYNC SSC Receive Frame Sync I/O
TX_CLOCK SSC Transmit Clock I/O
Level Comments
AT32AP7002
TX_DATA SSC Transmit Data Output
TX_FRAME_SYNC SSC Transmit Frame Sync I/O
DMA Controller - DMAC
DMARQ0 - DMARQ3 DMA Requests Input
Timer/Counter - TIMER0, TIMER1
A0 Channel 0 Line A I/O
A1 Channel 1 Line A I/O
A2 Channel 2 Line A I/O
B0 Channel 0 Line B I/O
B1 Channel 1 Line B I/O
B2 Channel 2 Line B I/O
CLK0 Channel 0 External Clock Input Input
CLK1 Channel 1 External Clock Input Input
CLK2 Channel 2 External Clock Input Input
Two-wire Interface - TWI
SCL Serial Clock I/O
SDA Serial Data I/O
Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3
32054AS-AVR32-02/07
13
Table 3-1. Signal Description List
Signal Name Function Type
CLK Clock I/O
CTS Clear To Send Input
RTS Request To Send Output
RXD Receive Data Input
TXD Transmit Data Output
Pulse Width Modulator - PWM
PWM0 - PWM3 PWM Output Pins Output
Universal Serial Bus Device - USB
DDM USB Device Port Data - Analog
DDP USB Device Port Data + Analog
AT32AP7002
Active
Level Comments
VBG USB bandgap Analog
Connected to a 6810 Ohm ± 0.5%
resistor to gound and a 10 pF
capacitor to ground.
32054AS-AVR32-02/07
14
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