ATMEL AT 32 AP 7001 Service Manual

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Features

• High Performance, Low Power AVR

– 210 DMIPS throughput at 150 MHz – 16 KB instruction cache and 16 KB data caches – Memory Management Unit enabling use of operating systems – Single-cycle RISC instruction set including SIMD and DSP instructions – Java Hardware Acceleration

• Multimedia Co-Processor

– Vector Multiplication Unit for video acceleration through color-space conversion

(YUV<->RGB), image scaling and filtering, quarter pixel motion compensation

• Multi-hierarchy bus system

– High-performance data transfers on separate buses for increased performance

• Data Memories

– 32KBytes SRAM

• External Memory Interface

– SDRAM, DataFlash™, SRAM, Multi Media Card (MMC), Secure Digital (SD), – Compact Flash, Smart Media, NAND Flash

• Direct Memory Access Controller

– External Memory access without CPU intervention

• Interrupt Controller

– Individually maskable Interrupts – Each interrupt request has a programmable priority and autovector address

• System Functions

– Power and Clock Manager – Crystal Oscillator with Phase-Lock-Loop (PLL) – Watchdog Timer – Real-time Clock

• 6 Multifunction timer/counters

– Three external clock inputs, I/O pins, PWM, capture and various counting

capabilities

• 4 Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– 115.2 kbps IrDA Modulation and Demodulation – Hardware and software handshaking

• 3 Synchronous Serial Protocol controllers

– Supports I2S, SPI and generic frame-based protocols

• Two-Wir e Inte rfac e

– Sequential Read/Write Operations, Philips’ I2C© compatible

• Image Sensor Interface

– 12-bit Data Interface for CMOS cameras

• Universal Serial Bus (USB) 2.0 High Speed (480 Mbps) Device

– On-chip Transceivers with physical interface

• 16-bit stereo audio DAC

– Sample rates up to 50 kHz

• On-Chip Debug System

– Nexus Class 3 – Full speed, non-intrusive data and program trace – Runtime control and JTAG interface

• Package/Pins

– AT32AP7001: 208-pin QFP/ 90 GPIO pins

• Power supplies

– 1.65V to1.95V VDDCORE – 3.0V to 3.6V VDDIO

32 32-Bit Microcontroller

AVR®32 32-bit Microcontroller

AT32AP7001

Preliminary

Summary

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1. Part Description

The AT32AP7001 is a complete System-on-chip application processor with an AVR32 RISC processor achieving 210 DMIPS running at 150 MHz. AVR32 is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high application performance.

AT32AP7001 implements a Memory Management Unit (MMU) and a flexible interrupt controller supporting modern operating systems and real-time operating systems. The processor also includes a rich set of DSP and SIMD instructions, specially designed for multimedia and telecom applications.

AT32AP7001 incorporates SRAM memories on-chip for fast and secure access. For applications requiring additional memory, external 16-bit SRAM is accessible. Additionally, an SDRAM controller provides off-chip volatile memory access as well as controllers for all industry standard off-chip non-volatile memories, like Compact Flash, Multi Media Card (MMC), Secure Digital (SD)-card, SmartCard, NAND Flash and Atmel DataFlash™.

The Direct Memory Access controller for all the serial peripherals enables data transfer between memories without processor intervention. This reduces the processor overhead when transferring continuous and large data streams between modules in the MCU.

The Timer/Counters includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.

AT32AP7001

A pixel co-processor provides color space conversions for images and video, in addition to a wide variety of hardware filter support

Synchronous Serial Controllers provide easy access to serial communication protocols, audio standards like AC'97, I2S, I2C© and various SPI modes. The modules support frame-based protocols, like VoIP SIP protocols.

The Java hardware acceleration implementation in AVR32 allows for a very high-speed Java byte-code execution. AVR32 implements Java instructions in hardware, reusing the existing RISC data path, which allows for a near-zero hardware overhead and cost with a very high performance.

The Image Sensor Interface supports cameras with up to 12-bit data buses and connects directly to the LCD interface through a separate bus.

PS2 connectivity is provided for standard input devices like mice and keyboards.

AT32AP7001 integrates a class 3 Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control.

The C-compiler is closely linked to the architecture and is able to utilize code optimization features, both for size and speed.

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2. Blockdiagram

Figure 2-1. Blockdiagram

TRST_N

TCK TDO

TDI

TMS

EVTI_N

D+

D-

DATA[11..0]

HSYNC VSYNC

PCLK

PA PB PC PD PE

XIN32

XOUT32

XIN0

XOUT0

XIN1

XOUT1

PLL0

PLL1

OSCEN_N

Parallel Input/Output Controllers

RESET_N

CMD

DATA[7..0]

32 KHz

OSC

OSC0

OSC1

PLL0 PLL1

INTERFACE

MCKO

MDO[5..0]

MSEO[1..0]

EVTO_N

INTERFACE

SENSOR

INTERFACE

INTRAM0 INTRAM1

A A

[

]

JTAG

USB

DMA

IMAGE

DMA CONTROLLER

AUDIO BITSTREAM

DAC

MULTIMEDIA CARD

INTERFACE

AC97 CONTROLLER

POWER

MANAGER

CLOCK

GENERATOR

CLOCK

CONTROLLER

SLEEP

CONTROLLER

RESET

CONTROLLER

NEXUS

CLASS 3

PBB

S M

HSB

HSB-PB BRIDGE

OCD

MEMORY MANAGEMENT UNIT

INSTR

CACHE

HIGH SPEED BUS MATRIX

SMM

CONFIGURATION REGISTERS BUS

HSB

HSB-PB

BRIDGE A

PBA

DMA

AP CPU

DATA

CACHE

HSB-HSB BRIDGE

PERIPHERAL

CONTROLLER

PDC

PERIPHERAL

PDC

INTERFACE 0/1

SYNCHRONOUS

PDC

CONTROLLER 0/1/2

TWO-WIRE

INTERFACE

PS2 INTERFACE

REAL TIME

COUNTER

WATCHDOG

DMA

USART0 USART1 USART2 USART3

SERIAL

TIMER

AT32AP7001

PIXEL COPROCESSOR

RAS, CAS,

SDWE, NANDOE, NANDWE,

SDCK,

SDCKE,

NWE3,

NWE1,

NWE0,

NWAIT SDCS,

CFRNW,

CFCE1, CFCE2,

NRD,

NCS[3,1,0],

ADDR[22..0]

DATA[15..0]

PA PB PC PD PE

Parallel Input/Output Controllers

NCS[5,4,2]

CONTROLLER & ECC)

ADDR[23..25]

(SDRAM & STATIC MEMORY

EXTERNAL BUS INTERFACE

DATA[31..16]

RXD TXD CLK

RTS, CTS

SCK

MISO, MOSI

NPCS0

NPCS[3..1]

TX_CLOCK, TX_FRAME_SYNC

TX_DATA

RX_CLOCK, RX_FRAME_SYNC

RX_DATA

SCL SDA

CLOCK[1..0]

DATA[1..0]

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CLK[2..0]

NMI_N

]

[

]

N S

[

TIMER/COUNTER 0/1

]

[

7 .

]

EXTERNAL

INTERRUPT

CONTROLLER

INTERRUPT

CONTROLLER

PULSE WIDTH MODULATION CONTROLLER

PWM0 PWM1

PWM2 PWM3

2.1 Processor and architecture

2.1.1 AVR32AP CPU

•

32-bit load/store AVR32B RISC architecture.

– Up to 15 general-purpose 32-bit registers. – 32-bit Stack Pointer, Program Counter and Link Register reside in register file. – Fully orthogonal instruction set. – Privileged and unprivileged modes enabling efficient and secure Operating Systems. – Innovative instruction set together with variable instruction length ensuring industry leading

code density. – DSP extention with saturating arithmetic, and a wide variety of multiply instructions. – SIMD extention for media applications.

• 7 stage pipeline allows one instruction per clock cycle for most instructions.

– Java Hardware Acceleration. – Byte, half-word, word and double word memory access. – Unaligned memory access. – Shadowed interrupt context for INT3 and multiple interrupt priority levels. – Dynamic branch prediction and return address stack for fast change-of-flow. – Coprocessor interface.

• Full MMU allows for operating systems with memory protection.

• 16Kbyte Instruction and 16Kbyte data caches.

– Virtually indexed, physically tagged. – 4-way associative. – Write-through or write-back.

• Nexus Class 3 On-Chip Debug system.

– Low-cost NanoTrace supported.

AT32AP7001

2.1.2 Pixel Coprocessor (PiCo)

Coprocessor coupled to the AVR32 CPU Core through the TCB Bus.

•

• Three parallel Vector Multiplication Units (VMU) where each unit can:

– Multiply three pixel components with three coefficients. – Add the products from the multiplications together. – Accumulate the result or add an offset to the sum of the products.

• Can be used for accelerating:

– Image Color Space Conversion.

•Configurable Conversion Coefficients.

• Supports packed and planar input and output formats.

• Supports subsampled input color spaces (i.e 4:2:2, 4:2:0).

– Image filtering/scaling.

• Configurable Filter Coefficients.

• Throughput of one sample per cycle for a 9-tap FIR filter.

• Can use the built-in accumulator to extend the FIR filter to more than 9-taps.

• Can be used for bilinear/bicubic interpolations.

– MPEG-4/H.264 Quarter Pixel Motion Compensation.

• Flexible input Pixel Selector.

– Can operate on numerous different image storage formats.

• Flexible Output Pixel Inserter.

– Scales and saturates the results back to 8-bit pixel values.

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– Supports packed and planar output formats.

• Configurable coefficients with flexible fixed-point representation.

2.1.3 Debug and Test system

IEEE1149.1 compliant JTAG and boundary scan

•

• Direct memory access and programming capabilities through JTAG interface

• Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 3

• Auxiliary port for high-speed trace information

• Hardware support for 6 Program and 2 data breakpoints

• Unlimited number of software breakpoints supported

• Advanced Program, Data, Ownership, and Watchpoint trace supported

2.1.4 DMA controller

2 HSB Master Interfaces

•

• 3 Channels

• Software and Hardware Handshaking Interfaces

– 11 Hardware Handshaking Interfaces

• Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer

• Single-block DMA Transfer

• Multi-block DMA Transfer

– Linked Lists – Auto-Reloading – Contiguous Blocks

• DMA Controller is Always the Flow Controller

• Additional Features

– Scatter and Gather Operations – Channel Locking

Bus Locking

– – FIFO Mode – Pseudo Fly-by Operation

AT32AP7001

2.1.5 Peripheral DMA Controller

Transfers from/to peripheral to/from any memory space without intervention of the processor.

•

• Next Pointer Support, forbids strong real-time constraints on buffer management.

• Eighteen channels

– Two for each USART – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface

2.1.6 Bus system

HSB bus matrix with 10 Masters and 8 Slaves handled

•

– Handles Requests from the CPU Icache, CPU Dcache, HSB bridge, HISI, USB 2.0 Controller,

DMA Controller 0, DMA Controller 1, and to internal SRAM 0, internal SRAM 1, PB A, PB B,

EBI and, USB.

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AT32AP7001

– Round-Robin Arbitration (three modes supported: no default master, last accessed default

master, fixed default master)

– Burst Breaking with Slot Cycle Limit – One Address Decoder Provided per Master

• 2 Peripheral buses allowing each bus to run on different bus speeds.

– PB A intended to run on low clock speeds, with peripherals connected to the PDC. – PB B intended to run on higher clock speeds, with peripherals connected to the DMAC.

• HSB-HSB Bridge providing a low-speed HSB bus running at the same speed as PBA

– Allows PDC transfers between a low-speed PB bus and a bus matrix of higher clock speeds

An overview of the bus system is given in Figure 2-1 on page 3. All modules connected to the same bus use the same clock, but the clock to each module can be individually shut off by the Power Manager. The figure identifies the number of master and slave interfaces of each module connected to the HSB bus, and which DMA controller is connected to which peripheral.

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3. Package and Pinout

3.1 AVR32AP7001

Figure 3-1. 208 QFP Pinout.

AT32AP7001

105156

157

208

104

152

Table 3-1. QFP-208 Package Pinout

1 GND 53 GND 105 GND 157 GND

2 PE17 54 PA23 106 PX13 158 PB10

3 PE18 55 PA24 107 PX14 159 PB11

4 PX47 56 XIN1 108 PX15 160 PB12

5 PX48 57 XOUT1 109 PX16 161 PB13

6 PX49 58 AVDDUSB 110 PX17 162 PB14

7 PX50 59 AGNDUSB 111 PX34 163 PB15

8 PX51 60 VDDIO 112 PX35 164 PB16

9 VDDIO 61 FSDM 113 PX36 165 PB17

10 PX32 62 FSDP 114 PX37 166 PB18

11 PX33 63 GND 115 PX38 167 PB19

12 PX00 64 GND 116 PX18 168 PB20

13 PX01 65 HSDM 117 PX19 169 PB21

14 PX02 66 HSDP 118 PX20 170 PB22

15 PX03 67 VDDCORE 119 PX21 171 PB23

16 PX04 68 GND 120 PX22 172 VDDCORE

17 PX05 69 GND 121 PX23 173 GND

18 VDDCORE 70 VBG 122 PX24 174 GND

19 GND 71 VDDIO 123 PX25 175 PA06

20 TDO 72 PA25 124 PX26 176 PA07

21 TCK 73 PA26 125 VDDIO 177 VDDIO

32015AS–AVR32–02/07

AT32AP7001

Table 3-1. QFP-208 Package Pinout (Continued)

22 TMS 74 PA27 126 PX27 178 VDDIO

23 TDI 75 PA28 127 PX28 179 OSCEN_N

24 TRST_N 76 PA29 128 PX29 180 XIN32

25 EVTI_N 77 PA30 129 PX30 181 XOUT32

26 RESET_N 78 PA31 130 PX31 182 AGNDOSC

27 PA00 79 WAKE_N 131 VDDCORE 183 AVDDOSC

28 PA01 80 PB26 132 GND 184 PLL1

29 PA02 81 PB27 133 GND 185 XIN0

30 PA03 82 PB28 134 PE26 186 XOUT0

31 PA04 83 PX53 135 PX39 187 AGNDPLL

32 PA05 84 PX52 136 VDDCORE 188 AVDDPLL

33 PB24 85 PX41 137 GND 189 PLL0

34 PB25 86 GND 138 PX40 190 PE00

35 PA08 87 PE25 139 PX42 191 PE01

36 VDDIO 88 PE24 140 PX43 192 PE02

37 GND 89 PE23 141 PX44 193 PE03

38 PA09 90 PE22 142 PX45 194 PE04

39 PA10 91 PE21 143 PX46 195 PE05

40 PA11 92 PE20 144 PB00 196 PE06

41 PA12 93 PE19 145 PB01 197 PE07

42 PA13 94 PX06 146 PB02 198 PE08

43 PA14 95 PX07 147 PB03 199 PE09

44 PA15 96 PX08 148 PB04 200 PE10

45 PA16 97 PX09 149 PB05 201 PE11

46 PA17 98 PX10 150 PB06 202 PE12

47 PA18 99 PX11 151 PB07 203 PE13

48 PA19 100 PB29 152 PB08 204 PE14

49 PA20 101 PB30 153 PB09 205 PE15

50 PA21 102 PX12 154 PC16 206 PE16

51 PA22 103 PC00 155 PC17 207 No Connect

52 VDDIO 104 VDDIO 156 VDDIO 208 GND

32015AS–AVR32–02/07

AT32AP7001

4. Signals Description

The following table gives details on the signal name classified by peripheral. The pinout multiplexing of these signals is given in the Peripheral Muxing table in the Peripherals chapter.

Table 4-1. Signal Description List

Active

Signal Name Function Type

Power

AVDDPLL PLL Power Supply Power 1.65 to 1.95 V

AVDDUSB USB Power Supply Power 1.65 to 1.95 V

AVDDOSC Oscillator Power Supply Power 1.65 to 1.95 V

VDDCORE Core Power Supply Power 1.65 to 1.95 V

VDDIO I/O Power Supply Power 3.0 to 3.6V

AGNDPLL PLL Ground Ground

AGNDUSB USB Ground Ground

Level Comments

AGNDOSC Oscillator Ground Ground

GND Ground Ground

Clocks, Oscillators, and PLL’s

XIN0, XIN1, XIN32 Crystal 0, 1, 32 Input Analog

XOUT0, XOUT1, XOUT32

PLL0, PLL1 PLL 0,1 Filter Pin Analog

TCK Test Clock Input

TDI Test Data In Input

TDO Test Data Out Output

TMS Test Mode Select Input

TRST_N Test Reset Input Low

MCKO Trace Data Output Clock Output

Crystal 0, 1, 32 Output Analog

JTAG

Auxiliary Port - AUX

MDO0 - MDO5 Trace Data Output Output

MSEO0 - MSEO1 Trace Frame Control Output

EVTI_N Event In Input Low

32015AS-AVR32-02/07

Table 4-1. Signal Description List

Active

Signal Name Function Type

EVTO_N Event Out Output Low

Power Manager - PM

GCLK0 - GCLK4 Generic Clock Pins Output

OSCEN_N Oscillator Enable Input Low

RESET_N Reset Pin Input Low

WAKE_N Wake Pin Input Low

External Interrupt Module - EIM

EXTINT0 - EXTINT3 External Interrupt Pins Input

NMI_N Non-Maskable Interrupt Pin Input Low

AC97 Controller - AC97C

Level Comments

AT32AP7001

SCLK AC97 Clock Signal Input

SDI AC97 Receive Signal Output

SDO AC97 Transmit Signal Output

SYNC AC97 Frame Synchronization Signal Input

DAC - DAC

DATA0 - DATA1 D/A Data Out Output

DATAN0 - DATAN1 D/A Inverted Data Out Output

External Bus Interface - EBI

ADDR0 - ADDR25 Address Bus Output

CAS Column Signal Output Low

CFCE1 Compact Flash 1 Chip Enable Output Low

CFCE2 Compact Flash 2 Chip Enable Output Low

CFRNW Compact Flash Read Not Write Output

DATA0 - DATA31 Data Bus I/O

NANDOE NAND Flash Output Enable Output Low

NANDWE NAND Flash Write Enable Output Low

NCS0 - NCS5 Chip Select Output Low

NRD Read Signal Output Low

32015AS-AVR32-02/07

Table 4-1. Signal Description List

Active

Signal Name Function Type

NWAIT External Wait Signal Input Low

NWE0 Write Enable 0 Output Low

NWE1 Write Enable 1 Output Low

NWE3 Write Enable 3 Output Low

RAS Row Signal Output Low

SDA10 SDRAM Address 10 Line Output

SDCK SDRAM Clock Output

SDCKE SDRAM Clock Enable Output

SDCS SDRAM Chip Select Output Low

SDWE SDRAM Write Enable Output Low

Level Comments

AT32AP7001

Image Sensor Interface - ISI

DATA0 - DATA11 Image Sensor Data Input

HSYNC Horizontal Synchronization Input

PCLK Image Sensor Data Clock Input

VSYNC Vertical Synchronization Input

Mulitmedia Card Interface - MMCI

CLK Multimedia Card Clock Output

CMD0 - CMD1 Multimedia Card Command I/O

DATA0 - DATA7 Multimedia Card Data I/O

Parallel Input/Output 2 - PIOA, PIOB, PIOC, PIOD, PIOE

PA0 - PA31 Parallel I/O Controller PIOA I/O

PB0 - PB30 Parallel I/O Controller PIOB I/O

PC0 - PC31 Parallel I/O Controller PIOC I/O

PD0 - PD17 Parallel I/O Controller PIOD I/O

PE0 - PE26 Parallel I/O Controller PIOE I/O

PS2 Interface - PSIF

CLOCK0 - CLOCK1 PS2 Clock Input

DATA0 - DATA1 PS2 Data I/O

32015AS-AVR32-02/07

Table 4-1. Signal Description List

Active

Signal Name Function Type

Serial Peripheral Interface - SPI0, SPI1

MISO Master In Slave Out I/O

MOSI Master Out Slave In I/O

NPCS0 - NPCS3 SPI Peripheral Chip Select I/O Low

SCK Clock Output

Synchronous Serial Controller - SSC0, SSC1, SSC2

RX_CLOCK SSC Receive Clock I/O

RX_DATA SSC Receive Data Input

RX_FRAME_SYNC SSC Receive Frame Sync I/O

TX_CLOCK SSC Transmit Clock I/O

Level Comments

AT32AP7001

TX_DATA SSC Transmit Data Output

TX_FRAME_SYNC SSC Transmit Frame Sync I/O

DMA Controller - DMAC

DMARQ0 - DMARQ3 DMA Requests Input

Timer/Counter - TIMER0, TIMER1

A0 Channel 0 Line A I/O

A1 Channel 1 Line A I/O

A2 Channel 2 Line A I/O

B0 Channel 0 Line B I/O

B1 Channel 1 Line B I/O

B2 Channel 2 Line B I/O

CLK0 Channel 0 External Clock Input Input

CLK1 Channel 1 External Clock Input Input

CLK2 Channel 2 External Clock Input Input

Two-wire Interface - TWI

SCL Serial Clock I/O

SDA Serial Data I/O

Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3

32015AS-AVR32-02/07

Table 4-1. Signal Description List

Signal Name Function Type

CLK Clock I/O

CTS Clear To Send Input

RTS Request To Send Output

RXD Receive Data Input

TXD Transmit Data Output

Pulse Width Modulator - PWM

PWM0 - PWM3 PWM Output Pins Output

Universal Serial Bus Device - USB

DDM USB Device Port Data - Analog

DDP USB Device Port Data + Analog

AT32AP7001

Active

Level Comments

VBG USB bandgap Analog

Connected to a 6810 Ohm ± 0.5% resistor to gound and a 10 pF capacitor to ground.

32015AS-AVR32-02/07

5. Power Considerations

5.1 Power Supplies

The AT32AP7001 has several types of power supply pins:

•

VDDCORE pins: Power the core, memories, and peripherals. Voltage is 1.8V nominal.

• VDDIO pins: Power I/O lines. Voltage is 3.3V nominal.

• VDDPLL pin: Powers the PLL. Voltage is 1.8V nominal.

• VDDUSB pin: Powers the USB. Voltage is 1.8V nominal.

• VDDOSC pin: Powers the oscillators. Voltage is 1.8V nominal.

The ground pins GND are common to VDDCORE and VDDIO. The ground pin for VDDPLL is GNDPLL, and the GND pin for VDDOSC is GNDOSC.

See ”Electrical Characteristics” on page 928 for power consumption on the various supply pins.

5.2 Power Supply Connections

Special considerations should be made when connecting the power and ground pins on a PCB.

Figure 5-1 shows how this should be done.

Figure 5-1. Connecting analog power supplies

AT32AP7001

AVDDUSB

AVDDPLL

AVDDOSC AGNDUSB

AGNDPLL

AGNDOSC

VDDCORE

3.3uH

C54

0.10u

VCC_1V8

C56

C55

0.10u

32015AS–AVR32–02/07

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