Atmel AT30TSE752A, AT30TSE754A, AT30TSE758A Datasheet

AT30TSE752A, AT30TSE754A, AT30TSE758A

9- to 12-bit Selectable, ±0.5°C Accurate

Digital Temperature Sensor with Nonvolatile Registers

and Serial EEPROM

DATASHEET

Features

 Integrated Temperature Sensor + Nonvolatile Registers + Serial EEPROM

 2-Wire I

 Single 1.7V to 5.5V supply

 400kHz and 1MHz compatibility

 Industry standard green (Pb/Halide-free/RoHS compliant) package options

2

C and SMBus™ compatible serial interface

 Supports SMBus Timeout
 Supports SMBus Alert and Alert Response Address (ARA)
 Selectable addressing allows up to eight devices on the same bus

 8-lead SOIC (150-mil)
 8-lead MSOP (3.0 x 3.0mm)
 8-pad Ultra Thin DFN (UDFN — 2.0 x 3.0 x 0.6mm)

Digital Temperature Sensor Features

 Measures temperature from -55C to +125C

 Highly accurate temperature measurements requiring no external components

 ±0.5°C accuracy (typical) over the 0C to +85C range
 ±1.0°C accuracy (typical) over the -25C to +105C range
 ±2.0°C accuracy (typical) over the -40C to +125C range

 Pin and software compatible to industry-standard LM75-type devices

 User-configurable resolution

 9 to 12 bits (0.5C to 0.0625C)

 User-configurable high and low temperature limits

 Nonvolatile registers to retain user-configured or pre-defined power-up defaults

 Register locking to prevent erroneous misconfiguration

 Register lockdown for permanent, non-changeable device configuration

 One-Shot mode for single temperature measurement while in Shutdown mode

 ALERT output pin for indicating temperature alarms

 Low power dissipation

 75μA active current (typical) during temperature measurements

 Shutdown mode to minimize power consumption

 1μA active current (typical)

Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014

Serial EEPROM Features

 Atmel

 Atmel AT30TSE754A Integrates 4Kb of EEPROM

 Atmel AT30TSE758A Integrates 8Kb of EEPROM

 Reversible software Write protection for full array

 Supports byte and Page Write operations

 Self-timed write cycle (5ms maximum)

 High-reliability

®

AT30TSE752A Integrates 2Kb of EEPROM

 Endurance: 1,000,000 write cycles
 Data retention: 100 years

2

AT30TSE752A/754A/758A [DATASHEET]

Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014

Table of Contents

1. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2. Pin Descriptions and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4. Device Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2 Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.3 Acknowledge (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.4 No-Acknowledge (NACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.1 Temperature Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2 Temperature Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2.1 Fault Tolerance Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2.2 Comparator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.2.3 Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.3 Shutdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3.1 One-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1 Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.2 Temperature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.3 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3.1 OS Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.3.2 R1:R0 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.3.3 FT1:FT0 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3.4 POL Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3.5 CMP/INT Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3.6 SD Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3.7 NVRBSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4 Nonvolatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.4.1 NVR1: NVR0 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.4.2 NVFT1:NVFT0 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4.3 NVPOL Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4.4 NVCMP/INT Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4.5 NVSD Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4.6 RLCKDWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4.7 RLCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.5 T

6.6 Nonvolatile T

LOW

and T

Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

HIGH

LOW

and T

Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 29

HIGH

7. Register Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8. Operations Allowed During Nonvolatile Busy Status . . . . . . . . . . . . . . . 33

9. Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9.1 Copy Nonvolatile Registers to Volatile Registers . . . . . . . . . . . . . . . . . . . . . . 34

9.2 Copy Volatile Registers to Nonvolatile Registers . . . . . . . . . . . . . . . . . . . . . . 35

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10. Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.1 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.2 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.3 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.3.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.3.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.3.3 Acknowledge Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10.4 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10.4.1 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10.4.2 Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10.4.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

10.5 Software Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11. SMBus Features and I2C General Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

11.1 SMBus Alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

11.2 SMBus Timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

11.3 General Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

12. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.2 DC and AC Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

12.4 Temperature Sensor Accuracy and Conversion Characteristics . . . . . . . . . . 46

12.5 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

12.6 Nonvolatile Register and Serial EEPROM Characteristics . . . . . . . . . . . . . . . 47

12.7 Power-Up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

12.8 Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12.9 Input Test Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . 48

12.10 Output Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

13.1 Atmel Ordering Code Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

13.2 Green Package Options (Pb/Halide-free/RoHS Compliant) . . . . . . . . . . . . . . 50

14. Part Marking Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

15. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

15.1 8S1 — 8-lead JEDEC SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

15.2 8XM — 8-lead MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

15.3 8MA2 — 8-pad UDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

16. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

16.1 No Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

17. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4

AT30TSE752A/754A/758A [DATASHEET]

Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014

1. Description

The Atmel® AT30TSE752A/754A/758A are a complete, precise temperature monitoring device designed for use in a
variety of applications that require the measuring of local temperatures as an integral part of the system's function and/or
reliability. The AT30TSE752A/754A/758A devices combine a high-precision digital temperature sensor, programmable
high and low temperature alarms, and a 2-wire I
into a single, compact package.

The temperature sensor can measure temperatures over the full -55°C to +125°C temperature range and has a typical
accuracy as precise as ±0.5°C from 0°C to +85°C. The result of the digitized temperature measurements are stored in
one of the AT30TSE752A/754A/758A's internal registers, which is readable at any time through the device's serial
interface.

The AT30TSE752A/754A/758A utilizes flexible, user-programmable internal registers to configure the temperature
sensor's performance and response to high and low temperature conditions. The device also contains a set of
Nonvolatile Registers to retain the configuration and temperature limit settings even after the device has been power
cycled, thereby eliminating the need for the device to be reconfigured after each Power-up operation. This additional
flexibility permits the device to run self-contained and not rely upon a host controller for device configuration.

In addition, the AT30TSE752A/754A/758A contain a 2Kb, 4Kb, or 8Kb Serial EEPROM that can be used to store vital
user system configuration and preference data. This additional feature permits the device to replace an existing
2-wire I

A dedicated alarm output activates if the temperature measurement exceeds the user-defined temperature and fault
count limits. To reduce current consumption and save power, the AT30TSE752A/754A/758A features a Shutdown mode
that turns off all internal circuitry except for the internal Power-On Reset (POR) and serial interface circuits. The device
can also be configured to power-up in the Shutdown mode to ensure that the device remains in a low-power state until
the user wishes to perform temperature measurements.

The AT30TSE752A/754A/758A are factory-calibrated and requires no external components to measure temperature.
With its flexibility and high-degree of accuracy, the AT30TSE752A/754A/758A are ideal for extended temperature
measurements in a wide variety of communication, computer, consumer, environmental, industrial, and instrumentation
applications.

2

C Serial EEPROM in an application saving board space and component cost.

2

C and SMBus (System Management Bus) compatible serial interface

AT30TSE752A/754A/758A [DATASHEET]

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2. Pin Descriptions and Pinouts

Table 1. Pin Description

Symbol Name and Function

SCL Serial Clock: This pin is used to provide a clock to the device and is used to control

the flow of data to and from the device. Command and input data present on the SDA
pin is always latched in on the rising edge of SCL, while output data on the SDA pin is
always clocked out on the falling edge of SCL.

The SCL pin must either be forced high when the serial bus is idle or pulled-high using
an external pull-up resistor.

SDA Serial Data: The SDA pin is an open-drain bidirectional input/output pin used to

serially transfer data to and from the device.

The SDA pin must be pulled-high using an external pull-up resistor and may be
wire-ANDed with any number of other open-drain or open-collector pins from other
devices on the same bus.

ALERT ALERT: The ALERT pin is an open-drain output pin used to indicate when the

temperature goes beyond the user-programmed temperature limits. The ALERT pin
can be operated in one of two different modes (Interrupt or Comparator mode) as
defined by the CMP/INT bit in the Configuration Register. The ALERT pin defaults to
an active-low output upon device power-up or reset but can be reconfigured as an
active-high output by setting the POL bit in the Configuration Register.

This pin can be wire-ANDed together with ALERT pins from other devices on the same
bus. When wire-ANDing pins together, the ALERT pin should be configured as an
active-low output so that when a single ALERT pin on the common alert bus goes
active, the entire common alert bus will go low and the host controller will be properly
notified since other ALERT pins that may be in the inactive-high state will not mask the
true alert signal. In an SMBus environment, the SMBus host can respond by sending
an SMBus ARA (Alert Response Address) command to determine which device on the
SMBus generated the alert signal.

The ALERT pin must be pulled-high using an external pull-up resistor even when it is
not used. Care must also be taken to prevent this pin from being shorted directly to
ground without a resistor at any time whether during testing or normal operation.

Asserted

State

— Input

— Input/Output

— Output

Type

A

2-0

Address Inputs: The A
to the three Least-Significant Bits (LSBs) of the I
pins can be directly connected in any combination to V
A

pins, up to eight devices may be addressed on a single bus.

2-0

The A

pins are internally pulled to GND and may be left floating; however, it is highly

2-0

recommended that the A

pins are used to select the device address and correspond

2-0

pins always be directly connected to VCC or GND to ensure

2-0

2

C/SMBus 7-bit slave address. These

CC

or GND, and by utilizing the

— Input

a known address state.

V

CC

Device Power Supply: The VCC pin is used to supply the source voltage to the device.

Operations at invalid V

voltages may produce spurious results and should not be

CC

— Power

attempted.

GND Ground: The ground reference for the power supply. GND should be connected to the

system ground.

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AT30TSE752A/754A/758A [DATASHEET]

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— Power

Figure 1. Pin Configurations

A

A

8-SOIC

(Top View)

SDA

SCL

LERT

GND

1

2

3

4

3. Block Diagram

Figure 3-1. Block Diagram

I2C/SMBus

SCL

SDA

Interface

Control

and

Logic

8

7

6

5

Pointer

Register

Nonvolatile

Configuration

Register

V

CC

A

0

A

1

A

2

Configuration

Register

SDA

SCL

ALERT

GND

Nonvolatile

T

HIGH

Register

Limit

8-MSOP

(Top View)

1

2

3

4

T

Limit

HIGH

Register

8-UDFN

(Top View)

ALERT

T

Limit

LOW

Register

SDA

SCL

GND

8

7

6

5

V

A

A

A

Nonvolatile

T

Limit

LOW

Register

CC

0

1

2

1

2

3

4

Temperature

Register

8

7

6

5

Converter

A/D

V

CC

A

0

A

1

A

2

A

LERT

2-0

3

Temperature

Sensor

Digital

Comparator

Serial

EEPROM

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4. Device Communication

The AT30TSE752A/754A/758A operates as a slave device and utilizes a simple 2-wire I2C and SMBus compatible digital
serial interface to communicate with a host controller, commonly referred to as the bus Master. The Master initiates and
controls all Read and Write operations to the slave devices on the serial bus, and both the Master and the slave devices
can transmit and receive data on the bus.

The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA). The SCL pin is used
to receive the clock signal from the Master, while the bidirectional SDA pin is used to receive command and data
information from the Master as well as to send data back to the Master. Data is always latched into the
AT30TSE752A/754A/758A on the rising edge of SCL and always output from the device on the falling edge of SCL. Both
the SCL and SDA pin incorporate integrated spike suppression filters and Schmitt triggers to minimize the effects of input
spikes and bus noise.

All command and data information is transferred with the Most-Significant Bit (MSB) first. During bus communication, one
data bit is transmitted every clock cycle, and after eight bits (one byte) of data has been transferred, the receiving device
must respond with either an acknowledge (ACK) or a no-acknowledge (NACK) response bit during a ninth clock cycle
(ACK/NACK clock cycle) generated by the Master. Therefore, nine clock cycles are required for every one byte of data
transferred. There are no unused clock cycles during any Read or Write operation, so there must not be any interruptions
or breaks in the data stream during each data byte transfer and ACK or NACK clock cycle.

During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain stable while
SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will occur. Start and
Stop conditions are used to initiate and end all serial bus communication between the Master and the slave devices. The
number of data bytes transferred between a Start and a Stop condition is not limited and is determined by the Master.

In order for the serial bus to be idle, both the SCL and SDA pins must be in the logic-high state at the same time.

4.1 Start Condition

A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is stable in the logic-high
state. The Master uses a Start condition to initiate any data transfer sequence, and the Start condition must precede any
command. The AT30TSE752A/754A/758A will continuously monitor the SDA and SCL pins for a Start condition, and the
device will not respond unless one is given.

4.2 Stop Condition

A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the logic-high
state. The Master uses the Stop condition to end a data transfer sequence to the AT30TSE752A/754A/758A which will
subsequently return to the idle state. The Master can also utilize a repeated Start condition instead of a Stop condition to
end the current data transfer if the Master will perform another operation.

4.3 Acknowledge (ACK)

After every byte of data received, the AT30TSE752A/754A/758A must acknowledge to the Master that it has successfully
received the data byte by responding with an ACK. This is accomplished by the Master first releasing the SDA line and
providing the ACK/NACK clock cycle (a ninth clock cycle for every byte). During the ACK/NACK clock cycle, the
AT30TSE752A/754A/758A must output a Logic 0 (ACK) for the entire clock cycle such that the SDA line must be stable
in the logic-low state during the entire high period of the clock cycle.

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AT30TSE752A/754A/758A [DATASHEET]

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4.4 No-Acknowledge (NACK)

When the AT30TSE752A/754A/758A are transmitting data to the Master, the Master can indicate that it is done receiving
data and wants to end the operation by sending a NACK response to the AT30TSE752A/754A/758A instead of an ACK
response. This is accomplished by the Master outputting a Logic 1 during the ACK/NACK clock cycle, at which point the
AT30TSE752A/754A/758A will release the SDA line so that the Master can then generate a Stop condition.

In addition, the AT30TSE752A/754A/758A can use a NACK to respond to the Master instead of an ACK for certain
invalid operation cases such as an attempt to write to a Read-only Register (e.g. an attempt to write to the Temperature
Register).

Figure 4-1. Start, Stop, and ACK

SCL

SDA

Start

Condition

Data
Change
Allowed

Data

Must be

Stable

1

Data
Change
Allowed

Data

Must be

Stable

28

Data
Change
Allowed

Data
Change
Allowed

Data

Must be

Stable

9

ACK

Stop

Condition

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5. Device Operation

Commands used to configure and control the operation of the AT30TSE752A/754A/758A are sent to the device from the
Master via the serial interface. Likewise, the Master can read the temperature data from the AT30TSE752A/754A/758A
via the serial interface; however, since multiple slave devices can reside on the serial bus, each slave device must have
its own unique 7-bit address so that the Master can access each device independently.

For the AT30TSE752A/754A/758A, the first four MSBs of its 7-bit address are the device type identifier and are fixed at
1001 for temperature sensor and 1010 for Serial EEPROM. The remaining three LSBs correspond to the states of the
hard-wired A

Example: If the A

In order for the Master to select and access the AT30TSE752A/754A/758A, the Master must first initiate a Start
condition. Following the Start condition, the Master must output the device address byte. The device address byte
consists of the 7-bit device address plus a Read/Write (R/
performing a Read or a Write to the AT30TSE752A/754A/758A. If the R/
reading data from the AT30TSE752A/754A/758A. Alternatively, if the R/
writing data to the AT30TSE752A/754A/758A.

Table 5-1. AT30TSE752A/754A/758A Address Byte

Function Device Type Identifier Device Address Read/Write

Temp Sensor 1 0 0 1 A2 A1 A0 R/W

address pins.

2-0

pins are connected to GND, then the 7-bit device address would be 1001000 or 1010000.

2-0

W) control bit, which indicates whether the Master will be

W control bit is a Logic 1, then the Master will be

W control bit is a Logic 0, then the Master will be

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Serial EEPROM 1 0 1 0 A2 A1 A0 R/W

Software Write Protection

(1)

0 1 1 0 A2 A1 A0 R/W

Note: 1. See Section 10.5, “Software Write Protect” on page 40 for more information.

If the 7-bit address sent by the Master matches that of the AT30TSE752A/754A/758A, then the device will respond with
an ACK after it has received the full address byte. If there is an address mismatch, then the AT30TSE752A/754A/758A
will respond with a NACK and return to the idle state.

5.1 Temperature Measurements

The AT30TSE752A/754A/758A utilizes a band-gap type temperature sensor with an internal sigma-delta Analog-to­Digital Converter (ADC) to measure and convert the temperature reading into a digital value with a selectable resolution
as high as 0.0625C. The measured temperature is calibrated in degrees Celsius; therefore, a lookup table or conversion
routine is necessary for applications that wish to deal in degrees Fahrenheit.

The result of the digitized temperature measurements are stored in the internal Temperature Register of the
AT30TSE752A/754A/758A, which is readable at any time through the device's serial interface. When in the normal
operating mode, the device performs continuous temperature measurements and updates the contents of the
Temperature Register (see Section 6.2, “Temperature Register” on page 17) after each analog-to-digital conversion.

The resolution of the temperature measurement data can be configured to 9, 10, 11, or 12 bits which corresponds to
temperature increments of 0.5C, 0.25C, 0.125C, and 0.0625C, respectively. Selecting the temperature resolution is
done by setting the R1 and R0 bits in the Configuration Register (see Section 6.3, “Configuration Register” on page 19).
The ADC conversion time does increase with each bit of higher resolution, so careful consideration should be given to
the resolution versus conversion time relationship. The resolution after device power-up or reset will revert to what was
previously selected using the NVR1 and NVR0 bits of the Nonvolatile Configuration Register bits prior to when the device
was powered-down or reset.

With 12 bits of resolution, the AT30TSE752A/754A/758A can theoretically measure a temperature range of 255C
(-128C to +127C); however, the device is only designed to measure temperatures over a range of -55C to +125C.

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5.2 Temperature Alarm

After the measured temperature value has been stored into the Temperature Register, the data will be compared with
both the high and low temperature limits defined by the values stored in the T
If the comparison results in a valid fault condition (see Section 5.2.1, “Fault Tolerance Limits” on page 11), then the
device will activate the ALERT output pin.

The polarity and function of the ALERT pin can be configured by using specific bits in the Configuration Register. The
polarity of the ALERT pin is controlled by the POL bit in the Configuration Register while the function of the ALERT pin
changes based on the Alarm Thermostat mode, which can be configured to either Comparator mode (see Section 5.2.2,

“Comparator Mode” on page 12) or Interrupt mode (see Section 5.2.3, “Interrupt Mode” on page 13) by using the

CMP/INT bit in the Configuration Register. After the device powers up or resets, the NVPOL and NVCMP/INT bits of the
Nonvolatile Configuration Register are automatically copied into the POL and CMP/INT bits of the Configuration
Register; therefore, the ALERT pin polarity and function will revert back to the settings defined by the NVPOL and
NVCMP/INT bits prior to when the device was powered-down or reset.

The value of the high temperature limit stored in the T
temperature limit stored in the T
ALERT pin will output erroneous results and will falsely signal temperature alarms.

5.2.1 Fault Tolerance Limits

A temperature fault occurs if the measured temperature meets or exceeds either the high temperature limit set by the

Limit Register or the low temperature limit set by the T

T

HIGH

environmental or temperature noise, the device incorporates a fault tolerance queue that requires consecutive
temperature faults to occur before resulting in a valid fault condition. The fault tolerance queue value is controlled by the
FT1 and FT0 bits in the Configuration Register and can be set to a single fault count of one or a count of two, four, or six
consecutive faults.

An internal counter that automatically increments after a temperature fault is used to determine if the fault tolerance
queue setting has been met. After incrementing the fault counter, the device will compare the count to the fault tolerance
queue setting to see if a valid fault condition should be triggered. Once a valid fault condition occurs, the device will
activate the ALERT output pin. If the most recent measured temperature does not meet or exceed the high or low
temperature limit, then the internal fault counter will be reset back to zero.

Figure 5-1 shows a sample temperature profile and how each temperature fault would impact the internal fault counter.

Limit Register and T

HIGH

Limit Register must be greater than the value of the low

HIGH

Limit Register in order for the ALERT function to work properly; otherwise, the

LOW

Limit Register. To prevent false alarms due to

LOW

Limit Register.

LOW

Figure 5-1. Fault Count Example

T

Limit

HIGH

Temperature

Limit

T

LOW

Temperature Measurements/Conversions

After the device powers up or resets, the NVFT1 and NVFT0 bits of the Nonvolatile Configuration Register are
automatically copied into the FT1 and FT0 bits of the Configuration Register; therefore, the Fault Tolerance Queue
setting will revert back to the settings defined by the NVFT1 and NVFT0 bits prior to when the device was powered-down
or reset.

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5.2.2 Comparator Mode

When the device operates in the Comparator mode, then the ALERT pin goes active if the measured temperature meets
or exceeds the high temperature limit set by the T
number of temperature faults has been reached). The ALERT pin will return to the inactive state after the measured
temperature drops below the T
fault condition. The ALERT pin only changes state based on the high and low temperature limits and fault conditions;
reading from or writing to any register or putting the device into Shutdown mode will not affect the state of the ALERT pin.
The high temperature limit set by the T
Limit Register in order for the ALERT pin to activate correctly.

If switching from Interrupt mode to Comparator mode while the ALERT pin is already active, then the ALERT pin will
remain active until the measured temperature is below the T
create a valid fault condition.

The ALERT pin will return to the inactive state if the device receives the General Call Reset command. When reset, the
contents of the Nonvolatile Configuration Register will be copied into the Configuration Register; therefore, the device
may or may not return to the Comparator mode depending on the setting of the NVCMP/INT bit in the Nonvolatile
Configuration Register.

Figure 5-2 illustrates both the active high and active low ALERT pin response for a sample temperature profile with the

device configured for the Comparator mode and a fault tolerance queue setting of two.

Figure 5-2. Comparator Mode (Fault Tolerance Queue = 2)

Limit Register and a valid fault condition exists (the consecutive

HIGH

Limit Register value the appropriate number of times to create a subsequent valid

LOW

Limit Register must be greater than the low temperature limit set by the T

HIGH

Limit Register value the appropriate number of times to

LOW

LOW

Limit

T

HIGH

Temperature

Limit

T

LOW

ALERT

(Active High, POL = 1)

ALERT

(Active Low, POL = 0)

Temperature Measurements/Conversions

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5.2.3 Interrupt Mode

Similar to the Comparator mode, when the device operates in the Interrupt mode, the ALERT pin will go active if the
measured temperature meets or exceeds the high temperature limit set by the T
condition exists (the consecutive number of temperature faults has been reached). Unlike the Comparator mode,
however, the ALERT pin will remain active until one of three normal operation events takes place: any one of the device's
registers is read, the device responds to an SMBus Alert Response Address (ARA), or the device is put into Shutdown
mode.

Once the ALERT pin returns to the inactive state, it will not go active again until the measured temperature drops below
the low temperature limit set by the T
ALERT pin will remain active until one of the device's registers is read, the device responds to an SMBus ARA, or the
device is placed into the Shutdown mode.

After the ALERT pin becomes inactive again, the cycle will repeat itself with the ALERT pin going active after the
measured temperature meets or exceeds the T
process is cyclical between T
clear, T

event, ALERT clear, T

HIGH

In order for the ALERT pin to normally become active for the first time in the Interrupt Mode, the first event must be a
T

temperature alarm event; therefore, even if the measured temperature initially starts off between the T

HIGH

limits and then drops below the T

T

LOW

go active. The high temperature limit set by the T
the T

Limit Register in order for the ALERT pin to activate correctly.

LOW

If switching from Comparator mode to Interrupt Mode while the ALERT pin is already active, then the ALERT pin will
remain active until it is cleared by one of the events already detailed: any one of the device's registers is read, the device
responds to an SMBus Alert Response Address (ARA), or the device is put into Shutdown Mode. The ALERT pin will
also return to the inactive state if the device receives the General Call Reset command. When reset, the contents of the
Nonvolatile Configuration Register will be copied into the Configuration Register; therefore, the device may or may not
return to the Interrupt mode depending on the setting of the NVCMP/INT bit in the Nonvolatile Configuration Register.

Figures 5-3 and Figure 5-4 show both the active high and active low ALERT pin response for a sample temperature

profile with the device configured for the Interrupt mode and a fault tolerance queue setting of two. Figure 5-4 illustrates
how the ALERT pin output would look if there was a longer delay between the ALERT trigger and the reading of a
register.

HIGH

LOW

and T

event, etc.).

LOW

LOW

Limit Register and a valid fault

HIGH

Limit Register for the appropriate number of consecutive faults. Again, the

Limit Register value for the proper number of consecutive faults. This

HIGH

temperature alarms (e.g. T

LOW

event, ALERT clear, T

HIGH

event, ALERT

LOW

HIGH

and

temperature limit and has met valid fault conditions, the ALERT pin will still not

Limit Register must be greater than the low temperature limit set by

HIGH

Figure 5-3. Interrupt Mode (Fault Tolerance Queue = 2)

Limit

T

HIGH

Temperature

T

Limit

LOW

ALERT

(Active High, POL = 1)

Read Register Read Register Read Register

ALERT

(Active Low, POL = 0)

Temperature Measurements/Conversions

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Figure 5-4. Interrupt Mode (Fault Tolerance Queue = 2) Delay Before Reading Register

Limit

T

HIGH

Temperature

T

Limit

LOW

(Active High, POL = 1)

ALERT

ALERT

(Active Low, POL = 0)

5.3 Shutdown Mode

To reduce current consumption and save power, the device features a Shutdown mode that disables all internal device
circuitry except for the serial interface and POR circuits. While in the Shutdown mode, the internal temperature sensor is
not active, so no temperature measurements will be made. Entering and exiting the Shutdown mode is controlled by the
SD bit in the Configuration Register.

Entering the Shutdown mode can affect the ALERT pin depending on the Alarm Thermostat mode. If the device is
configured to operate in the Interrupt mode, then the ALERT pin will go inactive when the device enters the Shutdown
mode; however, the ALERT pin will not change states if the device is operating in the Comparator mode.

The fault count information will not change when the device enters or exits the Shutdown mode; therefore, the number of
previous temperature faults recorded by the internal fault counter will be retained unless the device is power-cycled or
reset. When exiting the Shutdown mode, the ALERT pin will go active if operating in Interrupt mode, a valid fault
condition exists, and the T
followed by a T

The device can be powered-down while in the Shutdown mode so that it will remain in the Shutdown mode after the
subsequent Power-up operation. This is accomplished by setting the NVSD bit in the Nonvolatile Configuration Register
to the Logic 1 state prior to power-down. Upon power-up or reset, the device will first copy the contents of the Nonvolatile
Data Registers into the Volatile Data Registers, after which the device will perform a single temperature measurement
and store the result in the Temperature Register. After this process is complete, the device will re-enter the Shutdown
mode.

event when exiting Shutdown mode).

LOW

HIGH

and T

Read Register Read Register

Temperature Measurements/Conversions

event cycles are maintained (i.e. T

LOW

event before entering Shutdown mode

HIGH

5.3.1 One-Shot Mode

The AT30TSE752A/754A/758A features a One-Shot Temperature mode that allows the device to perform a single
temperature measurement while in the Shutdown mode. By keeping the device in the Shutdown mode and utilizing the
One-Shot mode, the AT30TSE752A/754A/758A can remain in a lower power state and only go active to take
temperature measurements on an as-needed basis. The internal fault counter will be updated when taking a temperature
measurement using the One-Shot mode; therefore, a valid fault condition can be generated by the One-Shot temperature
measurements. If operating in Comparator mode, then the fault condition will cause the ALERT pin to go either active or
inactive depending on if the fault condition is a result of a T
condition will cause the ALERT pin to pulse active for a short duration of time to indicate a T
occurred. The ALERT pin will then return to the inactive state.

The One-Shot mode is controlled using the OS bit in the Configuration Register (see Section 6.3.1, “OS Bit” on page 20).

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HIGH

or T

event. If operating in Interrupt mode, the fault

LOW

HIGH

or T

event has

LOW

6. Registers

The AT30TSE752A/754A/758A contains eight registers (a Pointer Register and seven data registers) that are used to
control the operational mode and performance of the temperature sensor, store the user-defined high and low
temperature limits, and store the digitized temperature measurements. All accesses to the device are performed using
these eight registers. In order to read from and write to one of the device's seven data registers, the user must first select
a desired data register by utilizing the Pointer Register.

The device incorporates both volatile and nonvolatile versions of the Configuration Register, the T
the T
Nonvolatile Data Registers into the Volatile Data Registers. Both the volatile and Nonvolatile Data Registers can be
modified separately provided that the registers are not locked or locked down; however, all temperature sensor related
operations, such as responses to high and low temperature conditions, are based on the settings stored in the volatile
versions of the registers only. Therefore, if the Nonvolatile Data Registers are updated with new values, then the
contents of the Nonvolatile Data Registers should be copied to the Volatile Data Registers (see Section 9.1, “Copy

Nonvolatile Registers to Volatile Registers” on page 34)

Table 6-1. Registers

Limit Register. Upon device power-up or reset, the AT30TSE752A/754A/758A will copy the contents of the

HIGH

Limit Register, and

LOW

Register Address

Pointer Register n/a W 8-bit 00h n/a

Temperature Register 00h R 16-bit 0000h n/a

Configuration Register 01h R/W 16-bit Copy of Nonvolatile Configuration Register n/a

T

Limit Register 02h R/W 16-bit Copy of Nonvolatile T

LOW

T

Limit Register 03h R/W 16-bit Copy of Nonvolatile T

HIGH

Nonvolatile Configuration Register 11h R/W 16-bit Last Programmed State 0000h

Nonvolatile T

Nonvolatile T

Limit Register 12h R/W 16-bit Last Programmed State 4B00h (75C)

LOW

Limit Register 13h R/W 16-bit Last Programmed State 5000h (80C)

HIGH

The Configuration Register, despite being 16-bits wide, is compatible to industry standard LM75-type temperature
sensors that use an 8-bit wide register in that only the first 8-bits of the Configuration Register need to be written to or
read from.

6.1 Pointer Register

The 8-bit Write-only Pointer Register is used to address and select which one of the device's seven data registers
(Temperature Register, Configuration Register, T
Register, Nonvolatile T

For Read operations from the AT30TSE752A/754A/758A, once the Pointer Register is set to point to a particular data
register, it remains pointed to that same data register until the Pointer Register value is changed.

Read/

Write

Limit Register, or Nonvolatile T

LOW

Size Power-on Default

Limit Register, T

LOW

Limit Register) will be read from or written to.

HIGH

Limit Register n/a

LOW

Limit Register n/a

HIGH

Limit Register, Nonvolatile Configuration

HIGH

Factory

Default

Example: If the user sets the Pointer Register to point to the Temperature Register, then all subsequent reads from

the device will output data from the Temperature Register until the Pointer Register value is changed.

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For Write operations to the AT30TSE752A/754A/758A, the Pointer Register value must be refreshed each time a Write
to the device is to be performed, even if the same data register is going to be written to a second time in a row.

Example: If the Pointer Register is set to point to the Configuration Register, once the subsequent Write operation to

the Configuration Register has completed, the user cannot write again into the Configuration Register
without first setting the Pointer Register value again. As long as a Write operation is to be performed, the
device will assume that the Pointer Register value is the first data byte received after the address byte.

Since only seven data registers are available for access, only the five LSBs (P4-P0) of the Pointer Register are used; the
remaining three bits (P7-P5) of the Pointer Register should always be set to zero to allow for future migration paths to
other temperature sensor devices that have more than seven data registers. In addition, the device incorporates
additional commands that are decoded in lieu of the Pointer Register byte; therefore, if bits P7-P5 are not set as zero
when setting the value of the Pointer Register byte, the device may interpret the data as one of the additional commands.

Table 6-2 shows the bit assignments of the Pointer Register and the associated pointer addresses of the data registers

available. Attempts to write any values other than those listed in Table 6-2 into the Pointer Register will be ignored by the
device, and the contents of the Pointer Register will not be changed. The device will respond back to the Master with a
NACK to indicate that the device received an invalid Pointer Register byte.

Table 6-2. Pointer Register and Address Assignments

Pointer Register Value

Associated

Address

Register SelectedP7 P6 P5 P4 P3 P2 P1 P0

0 0 0 0 0 0 0 0 00h Temperature Register

0 0 0 0 0 0 0 1 01h Configuration Register

0 0 0 0 0 0 1 0 02h T

0 0 0 0 0 0 1 1 03h T

Limit Register

LOW

Limit Register

HIGH

0 0 0 1 0 0 0 1 11h Nonvolatile Configuration Register

0 0 0 1 0 0 1 0 12h Nonvolatile T

0 0 0 1 0 0 1 1 13h Nonvolatile T

Limit Register

LOW

Limit Register

HIGH

To set the value of the Pointer Register, the Master must first initiate a Start condition followed by the
AT30TSE752A/754A/758A device address byte (1001AAA0 where “AAA” corresponds to the hard-wired A

address

2-0

pins). After the AT30TSE752A/754A/758A has received the proper address byte, the device will send an ACK to the
Master. The Master must then send the appropriate data byte to the AT30TSE752A/754A/758A to set the value of the
Pointer Register.

After device power-up or reset, the Pointer Register defaults to 00h which is the Temperature Register location;
therefore, the Temperature Register can be read from immediately after device power-up or reset without having to set
the Pointer Register. If the device is configured to power-up in the Shutdown mode, then the device will make a single
temperature measurement immediately after power-up so that valid temperature data can be output from the
Temperature Register.

16

Figure 6-1. Write Pointer Register

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SCK

Address Byte Pointer Register Byte

SDA

Start

by

Master

1 0 0 1 A A A 0 0 P7 P6 P5 P4 P3 P2 P1 P0 0

MSB MSB

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ACK
from

Slave

ACK
from

Slave

Stop

by

Master

6.2 Temperature Register

The Temperature Register is a 16-bit Read-only Register that stores the digitized value of the most recent temperature
measurement. The temperature data value is represented in the twos complement format, and, depending on the
resolution selected, up to 12 bits of data will be available for output with the remaining LSBs being fixed in the Logic 0
state. The Temperature Register can be read at any time, and since temperature measurements are performed in the
background, reading the Temperature Register does not affect any other operation that may be in progress.

The MSB (bit 15) of the Temperature Register contains the sign bit of the measured temperature value with a zero
indicating a positive number and a one indicating a negative number. The remaining MSBs of the Temperature Register
contain the temperature value in the twos complement format. Table 6-3 details the Temperature Register format for the
different selectable resolutions, and Table 6-4 shows some examples for 12-bit resolution Temperature Register data
values and the associated temperature readings.

Table 6-3. Temperature Register Format

Upper Byte Lower Byte

Resolution

12 bits Sign TD TD TD TD TD TD TD TD TD TD TD 0 0 0 0

11 bits Sign TD TD TD TD TD TD TD TD TD TD 0 0 0 0 0

10 bits Sign TD TD TD TD TD TD TD TD TD 0 0 0 0 0 0

9 bits Sign TD TD TD TD TD TD TD TD 0 0 0 0 0 0 0

Note: TD = Temperature Data

Table 6-4. 12-bit Resolution Temperature Data/Values Examples

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Temperature Register Data

Temperature

+125°C 0111 1101 0000 0000 7D00h

+100°C 0110 0100 0000 0000 6400h

+75°C 0100 1011 0000 0000 4B00h

+50.5°C 0011 0010 1000 0000 3280h

+25.25°C 0001 1001 0100 0000 1940h

Binary Value Hex Value

+10.125°C 0000 1010 0010 0000 0A20h

+0.0625°C 0000 0000 0001 0000 0010h

0°C 0000 0000 0000 0000 0000h

-0.0625°C 1111 1111 1111 0000 FFF0h

-10.125°C 1111 0101 1110 0000 F5E0h

-25.25°C 1110 0110 1100 0000 E6C0h

-50.5°C 1100 1101 1000 0000 CD80h

-55°C 1100 1001 0000 0000 C900h

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17

After each temperature measurement and digital conversion is complete, the new temperature data is loaded into the
Temperature Register if the register is not currently being read. If a Read is in progress, then the previous temperature
data will be output. Accessing the Temperature Register continuously without waiting the maximum conversion time

) for the selected resolution may prevent the device from properly updating the Temperature Register with new

(t

CONV

temperature data.

In order to read the most recent temperature measurement data, the Pointer Register must be set or have been
previously set to 00h. If the Pointer Register has already been set to 00h, the Temperature Register can be read by
having the Master first initiate a Start condition followed by the AT30TSE752A/754A/758A device address byte
(1001AAA1 where “AAA” corresponds to the hard-wired A

address pins). After the AT30TSE752A/754A/758A has

2-0

received the proper address byte, the device will send an ACK to the Master. The Master can then read the upper byte of
the Temperature Register. After the upper byte of the Temperature Register has been clocked out of the
AT30TSE752A/754A/758A, the Master must send an ACK to indicate that it is ready for the lower byte of the temperature
data. The AT30TSE752A/754A/758A will then clock out the lower byte of the Temperature Register, after which the
Master must send a NACK to end the operation. When the AT30TSE752A/754A/758A receives the NACK, it will release
the SDA line so that the Master can send a Stop or repeated Start condition. If the Master does not send a NACK but
instead sends an ACK after the lower byte of the Temperature Register has been clocked out, then the device will repeat
the sequence by outputting new temperature data starting with the upper byte of the Temperature Register.

If 8-bit temperature resolution is satisfactory, then the lower byte of the Temperature Register does not need to be read.
In this case, the Master would send a NACK instead of an ACK after the upper byte of the Temperature Register has
been clocked out of the AT30TSE752A/754A/758A. When the AT30TSE752A/754A/758A receives the NACK, the device
will know that it should not send out the lower byte of the Temperature Register and will instead release the SDA line so
the Master can send a Stop or repeated Start condition.

The Temperature Register defaults to 0000h after device power-up or reset; therefore, the system should wait the
maximum conversion time (t

) for the selected resolution before attempting to read valid temperature data. If the

CONV

device is configured to power-up in the Shutdown mode, then the device will make a single temperature measurement
immediately after power-up so that valid temperature data can be output from the Temperature Register after the
maximum t

time. Since the Temperature Register is a Read-only Register, any attempts to write to the register will

CONV

be ignored, and the device will subsequently respond by sending a NACK back to the Master for any data bytes that are
sent.

Figure 6-2. Read Temperature Register — 16 Bits

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SCK

Address Byte Temperature Register Upper Byte Temperature Register Lower Byte

SDA

Start

Master

1 0 0 1 A A A 1 0 D15 D14 D13 D12 D11 D10 D9 D8 0 D7 D6 D5 D4 D3 D2 D1 D0 1

MSB

by

ACK
from

Slave

MSB

ACK
from

Master

MSB

Note: Assumes the Pointer Register was previously set to point to the Temperature Register.

Figure 6-3. Read Temperature Register — 8 Bits

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SCK

Address Byte Temperature Register Upper Byte

SDA

Start

Master

Note: Assumes the Pointer Register was previously set to point to the Temperature Register.

1 0 0 1 A A A 1 0 D15 D14 D13 D12 D11 D10 D9 D8 1

MSB MSB

by

ACK
from

Slave

NACK

from

Master

Stop

by

Master

NACK

from

Master

Stop

by

Master

18

AT30TSE752A/754A/758A [DATASHEET]

Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014