ATMEL AT29LV512 User Manual

Features

• Single Supply Voltage, Range 3V to 3.6V

• 3-volt Only Read and Write Operation

• Software Protected Programming

• Low-power Dissipation

– 15 mA Active Current
– 40 µA CMOS Standby Current

• Fast Read Access Time – 120 ns

• Sector Program Operation

– Single-cycle Reprogram (Erase and Program)
– 512 Sectors (128 Bytes/Sector)
– Internal Address and Data Latches for 128 Bytes

• Fast Sector Program Cycle Time – 20 ms Max

• Internal Program Control and Timer

• DATA Polling for End of Program Detection

• Typical Endurance > 10,000 Cycles

• CMOS and TTL Compatible Inputs and Outputs

• Commercial and Industrial Temperature Ranges

• Green (Pb/Halide-free) Packaging Option

1. Description

The AT29LV512 is a 3-volt-only in-system Flash programmable erasable read-only
memory (PEROM). Its 512K of memory is organized as 65,536 words by 8 bits. Man­ufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 120 ns with power dissipation of just 54 mW over the commercial tem­perature range. When the device is deselected, the CMOS standby current is less
than 40 µA. The device endurance is such that any sector can typically be written to in
excess of 10,000 times.

512K (64K x 8)
3-volt Only
Flash Memory

AT29LV512

To allow for simple in-system reprogrammability, the AT29LV512 does not require
high input voltages for programming. Three-volt-only commands determine the opera­tion of the device. Reading data out of the device is similar to reading from an
EPROM. Reprogramming the AT29LV512 is performed on a sector basis; 128 bytes
of data are loaded into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 128 bytes of data are captured at
microprocessor speed and internally latched, freeing the address and data bus for
other operations. Following the initiation of a program cycle, the device will automati­cally erase the sector and then program the latched data using an internal control
timer. The end of a program cycle can be detected by DATA
end of a program cycle has been detected, a new access for a read or program can
begin.

polling of I/O7. Once the

0177N–FLASH–2/05

2. Pin Configurations

Pin Name Function

A0 - A15 Addresses

CE

OE

WE

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

2.1 32-lead PLCC Top View

A7
A6
A5
A4
A3
A2
A1
A0

I/O0

Chip Enable

Output Enable

Write Enable

A12

A15NCNC

432

5
6
7
8
9
10
11
12
13

14151617181920

I/O1

I/O2

GND

1

I/O3

VCCWENC

323130

29
28
27
26
25
24
23
22
21

I/O4

I/O5

I/O6

A14
A13
A8
A9
A11
OE
A10
CE
I/O7

2.2 32-lead TSOP (Type 1) Top View

A11

A9

A8
A13
A14

NC

WE

VCC

NC

NC
A15
A12

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE

32

A10

31

CE

30

I/O7

29

I/O6

28

I/O5

27

I/O4

26

I/O3

25

GND

24

I/O2

23

I/O1

22

I/O0

21

A0

20

A1

19

A2

18

A3

17

2

AT29LV512

0177N–FLASH–2/05

3. Block Diagram

4. Device Operation

4.1 Read

The AT29LV512 is accessed like an EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state whenever CE
line control gives designers flexibility in preventing bus contention.

AT29LV512

or OE is high. This dual-

4.2 Software Data Protection Programming

The AT29LV512 has 512 individual sectors, each 128 bytes. Using the software data protection
feature, byte loads are used to enter the 128 bytes of a sector to be programmed. The
AT29LV512 can only be programmed or reprogrammed using the software data protection fea­ture. The device is programmed on a sector basis. If a byte of data within the sector is to be
changed, data for the entire 128-byte sector must be loaded into the device. The AT29LV512
automatically does a sector erase prior to loading the data into the sector. An erase command is
not required.

Software data protection protects the device from inadvertent programming. A series of three
program commands to specific addresses with specific data must be presented to the device
before programming may occur. After writing the three-byte command sequence (and after t
the entire device is protected. The same three program commands must begin each program
operation. All software program commands must obey the sector program timing specifications.
Power transitions will not reset the software data protection feature; however, the software fea­ture will guard against inadvertent program cycles during power transitions.

Any attempt to write to the device without the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however, for the duration of t
tion will effectively be a polling operation.

After the software data protection’s 3-byte command code is given, a byte load is performed by
applying a low pulse on the WE
address is latched on the falling edge of CE
the first rising edge of CE

or WE.

),

WC

, a read opera-

WC

or CE input with CE or WE low (respectively) and OE high. The

or WE, whichever occurs last. The data is latched by

0177N–FLASH–2/05

3

The 128 bytes of data must be loaded into each sector. Any byte that is not loaded during the
programming of its sector will be erased to read FFh. Once the bytes of a sector are loaded into
the device, they are simultaneously programmed during the internal programming period. After
the first data byte has been loaded into the device, successive bytes are entered in the same
manner. Each new byte to be programmed must have its high-to-low transition on WE
within 150 µs of the low-to-high transition of WE
transition is not detected within 150 µs of the last low-to-high transition, the load period will end
and the internal programming period will start. A7 to A15 specify the sector address. The sector
address must be valid during each high-to-low transition of WE
byte address within the sector. The bytes may be loaded in any order; sequential loading is not
required. Once a programming operation has been initiated, and for the duration of t
operation will effectively be a polling operation.

4.3 Hardware Data Protection

Hardware features protect against inadvertent programs to the AT29LV512 in the following
ways: (a) V
power on delay – once VCC has reached the VCC sense level, the device will automatically time
out 10 ms (typical) before programming; (c) Program inhibit – holding any one of OE
high or WE high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical)
on the WE

CC

or CE inputs will not initiate a program cycle.

4.4 Input Levels

While operating with a 3.3V ±10% power supply, the address inputs and control inputs (OE, CE
and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device.
The I/O lines can only be driven from 0 to 3.6 volts.

(or CE)

(or CE) of the preceding byte. If a high-to-low

(or CE). A0 to A6 specify the

, a read

WC

sense – if VCC is below 1.8V (typical), the program function is inhibited; (b) V

low, CE

CC

4.5 Product Identification

The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product.
In addition, users may wish to use the software product identification mode to identify the part
(i.e., using the device code), and have the system software use the appropriate sector size for
program operations. In this manner, the user can have a common board design for 256K to
4-megabit densities and, with each density’s sector size in a memory map, have the system soft­ware apply the appropriate sector size.

For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.

4.6 DATA Polling

The AT29LV512 features DATA polling to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in the complement of the loaded data
on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the
next cycle may begin. DATA

polling may begin at any time during the program cycle.

4

AT29LV512

0177N–FLASH–2/05

4.7 Toggle Bit

In addition to DATA polling, the AT29LV512 provides another method for determining the end of
a program or erase cycle. During a program or erase operation, successive attempts to read
data from the device will result in I/O6 toggling between one and zero. Once the program cycle
has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may
begin at any time during a program cycle.

4.8 Optional Chip Erase Mode

The entire device can be erased by using a 6-byte software code. Please see Software Chip
Erase application note for details.

5. Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

+ 0.6V

CC

AT29LV512

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability

Voltage on A9 (including NC Pins)

with Respect to Ground...................................-0.6V to +13.5V

0177N–FLASH–2/05

5

6. DC and AC Operating Range

AT29LV512-12 AT29LV512-15 AT29LV512-20 AT29LV512-25

Operating
Temperature (Case)

V

Power Supply

CC

Com. 0°C - 70°C 0°C - 70°C

Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C

(1)

3.3V ± 0.3V 3.3V ± 0.3V 3.3V ± 0.3V 3.3V ± 0.3V

0°C - 70°C 0°C - 70°C

Notes: 1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an

operational mode is started.

2.

Not recommended for New Designs.

7. Operating Modes

Mode CE OE WE Ai I/O

Read V

Program

(2)

Standby/Write Inhibit V

IL

V

IL

IH

Program Inhibit X X V

Program Inhibit X V

Output Disable X V

Product Identification

Hardware V

Software

Notes: 1. X can be V

(5)

or VIH.

IL

IL

2. Refer to AC Programming Waveforms.

3. VH = 12.0V ± 0.5V.

4. Manufacturer Code is 1F. The Device Code is 3D.

5. See details under Software Product Identification Entry/Exit.

X

V

IL

V

IH

(1)

IL

IH

V

IL

V

IH

V

IL

Ai D

Ai D

OUT

X X High Z

IH

X

X High Z

IL

IH

(3)

H

(3)

H

, A0 = V

, A0 = V

Manufacturer Code

IL

IH

Device Code

Manufacturer Code

Device Code

V

IH

A1 - A15 = VIL, A9 = V

A0 = V

A0 = V

A1 - A15 = VIL, A9 = V

IN

(4)

(4)

(4)

(4)

8. DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

CC

V

IL

V

IH

V

OL

V

OH

6

Input Load Current VIN = 0V to V

Output Leakage Current V

= 0V to V

I/O

CC

CC

1µA

1µA

Com. 40 µA

VCC Standby Current CMOS CE = V

VCC Standby Current TTL CE = 2.0V to V

V

Active Current f = 5 MHz; I

CC

- 0.3V to V

CC

OUT

CC

CC

Ind. 50 µA

1mA

= 0 mA; VCC = 3.6V 15 mA

Input Low Voltage 0.6 V

Input High Voltage 2.0 V

Output Low Voltage IOL = 1.6 mA; VCC = 3.0V 0.45 V

Output High Voltage IOH = -100 µA; VCC = 3.0V 2.4 V

AT29LV512

0177N–FLASH–2/05

9. AC Read Characteristics

Symbol Parameter

AT29LV512

AT29LV512-12 AT29LV512-15 AT29LV512-20 AT29LV512-25

UnitsMin Max Min Max Min Max Min Max

t

ACC

(1)

t

CE

(2)

t

OE

(3)(4)

t

DF

t

OH

Note:

Address to Output Delay 120 150 200 250 ns

CE to Output Delay 120 150 200 250 ns

OE to Output Delay 0 50 0 70 0 100 0 120 ns

CE or OE to Output Float 0 30 0 40 0 50 0 60 ns

Output Hold from OE, CE or
Address, whichever occurred first

Not recommended for New Designs.

10. AC Read Waveforms

Notes: 1. CE may be delayed up to t

2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by t
without impact on t

is specified from OE or CE whichever occurs first (CL = 5 pF).

3. t

DF

4. This parameter is characterized and is not 100% tested.

ACC

.

00

(1)(2)(3)(4)

- tCE after the address transition without impact on t

ACC

0 0 ns

.

ACC

- tOE after an address change

ACC

11. Input Test Waveforms and Measurement Level

tR, tF < 5 ns

12. Output Test Load

0177N–FLASH–2/05

7

13. Pin Capacitance

f = 1 MHz, T = 25°C

Symbol Typ Max Units Conditions

C

IN

C

OUT

Note: 1. These parameters are characterized and not 100% tested.

(1)

46pFV

812pFV

IN

OUT

= 0V

= 0V

14. AC Byte Load Characteristics

Symbol Parameter Min Max Units

t

AS

t

AH

t

CS

t

CH

t

WP

t

DS

t

DH

t

WPH

, t

OES

, t

OEH

Address, OE Set-up Time 0 ns

Address Hold Time 100 ns

Chip Select Set-up Time 0 ns

Chip Select Hold Time 0 ns

Write Pulse Width (WE or CE)200ns

Data Set-up Time 100 ns

Data, OE Hold Time 10 ns

Write Pulse Width High 200 ns

15. AC Byte Load Waveforms

15.1 WE Controlled

15.2 CE

Controlled

(1)(2)

8

AT29LV512

0177N–FLASH–2/05

AT29LV512

16. Program Cycle Characteristics

Symbol Parameter Min Max Units

t

WC

t

AS

t

AH

t

DS

t

DH

t

WP

t

BLC

t

WPH

Write Cycle Time 20 ms

Address Set-up Time 0 ns

Address Hold Time 100 ns

Data Set-up Time 100 ns

Data Hold Time 10 ns

Write Pulse Width 200 ns

Byte Load Cycle Time 150 µs

Write Pulse Width High 200 ns

17. Software Protected Program Waveform

(1)(2)(3)

Notes: 1. OE must be high when WE and CE are both low.

2. A7 through A15 must specify the sector address during each high-to-low transition of WE (or CE) after the software code
has been entered.

3. All bytes that are not loaded within the sector being programmed will be indeterminate.

18. Programming Algorithm

(1)

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA A0

TO

ADDRESS 5555

LOAD DATA

TO

SECTOR (128 BYTES)

WRITES ENABLED

ENTER DATA

(3)

PROTECT STATE

Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex).

2. Data Protect state will be re-activated at end of program cycle.

3. 128 bytes of data MUST BE loaded.

(2)

0177N–FLASH–2/05

9

19. Data Polling Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

WR

Data Hold Time 10 ns

OE Hold Time 10 ns

OE to Output Delay

(2)

Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec in AC Read Characteristics.

20. Data Polling Waveforms

ns

21. Toggle Bit Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

OEHP

t

WR

Data Hold Time 10 ns

OE Hold Time 10 ns

OE to Output Delay

(2)

OE High Pulse 150 ns

Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t

22. Toggle Bit Waveforms

spec in AC Read Characteristics.

OE

(1)(3)

ns

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

10

AT29LV512

0177N–FLASH–2/05

AT29LV512

23. Software Product Identification Entry

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA 90

TO

ADDRESS 5555

PAUSE 20 mS ENTER PRODUCT

(1)

IDENTIFICATION
MODE

Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex).

2. A1 - A15 = V

. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH.

IL

3. The device does not remain in identification mode if powered down.

4. The device returns to standard operation mode.

5. Manufacturer Code is 1F. The Device Code is 3D.

(2)(3)(5)

24. Software Product Identification Exit

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA F0

TO

ADDRESS 5555

PAUSE 20 mS EXIT PRODUCT

(1)

IDENTIFICATION

(4)

MODE

0177N–FLASH–2/05

11

25. Ordering Information

25.1 Standard Package

I

t

ACC

(ns)

120 15 0.04 AT29LV512-12JC

150 15 0.04 AT29LV512-15JC

200 15 0.04 AT29LV512-20JC

250 15 0.04 AT29LV512-25JC

(mA)

CC

Ordering Code Package Operation RangeActive Standby

AT29LV512-12TC

15 0.05 AT29LV512-12JI

AT29LV512-12TI

AT29LV512-15TC

15 0.05 AT29LV512-15JI

AT29LV512-15TI

AT29LV512-20TC

15 0.05 AT29LV512-20JI

AT29LV512-20TI

AT29LV512-25TC

15 0.05 AT29LV512-25JI

AT29LV512-25TI

32J
32T

32J
32T

32J
32T

32J
32T

32J
32T

32J
32T

32J
32T

32J
32T

Commercial
(0° to 70°C)

Industrial

(-40° to 85°C)

Commercial
(0° to 70°C)

Industrial

(-40° to 85°C)

Commercial
(0° to 70°C)

Industrial

(-40° to 85°C)

Commercial
(0° to 70°C)

Industrial

(-40° to 85°C)

Note:

Not recommended for New Designs.

25.2 Green Package Option (Pb/Halide-free)

I

t

ACC

(ns)

120 15 0.05 AT29LV512-12JU

150 15 0.05 AT29LV512-15JU

32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)

CC

(mA)

Ordering Code Package Operation RangeActive Standby

AT29LV512-12TU

AT29LV512-15TU

Package Type

32J
32T

32J
32T

Industrial

(-40° to 85°C)

Industrial

(-40° to 85°C)

32T 32-lead, Thin Small Outline Package (TSOP)

12

AT29LV512

0177N–FLASH–2/05

26. Packaging Information

26.1 32J – PLCC

AT29LV512

1.14(0.045) X 45˚

B

e

0.51(0.020)MAX

45˚ MAX (3X)

Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.

2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.

3. Lead coplanarity is 0.004" (0.102 mm) maximum.

PIN NO. 1
IDENTIFIER

D1

D

D2

1.14(0.045) X 45˚

E1 E

0.318(0.0125)

0.191(0.0075)

E2

B1

A2

A1

A

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A 3.175 – 3.556

A1 1.524 – 2.413

A2 0.381 – –

D 12.319 – 12.573

D1 11.354 – 11.506 Note 2

D2 9.906 – 10.922

E 14.859 – 15.113

E1 13.894 – 14.046 Note 2

E2 12.471 – 13.487

B 0.660 – 0.813

B1 0.330 – 0.533

e 1.270 TYP

MIN

NOM

MAX

NOTE

10/04/01

2325 Orchard Parkway

R

San Jose, CA 95131

0177N–FLASH–2/05

TITLE

32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)

DRAWING NO.

32J

REV.

B

13

26.2 32T – TSOP

PIN 1

Pin 1 Identifier

D1

D

e

E

b

A2

A

SEATING PLANE

A1

Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.

2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

0º ~ 8º

L

COMMON DIMENSIONS

SYMBOL

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 19.80 20.00 20.20

D1 18.30 18.40 18.50 Note 2

E 7.90 8.00 8.10 Note 2

L 0.50 0.60 0.70

L1 0.25 BASIC

b 0.17 0.22 0.27

c 0.10 – 0.21

e 0.50 BASIC

MIN

c

L1

GAGE PLANE

(Unit of Measure = mm)

NOM

MAX

NOTE

14

2325 Orchard Parkway

R

San Jose, CA 95131

AT29LV512

TITLE

32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline

Package, Type I (TSOP)

DRAWING NO.

32T

0177N–FLASH–2/05

10/18/01

REV.

B

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0177N–FLASH–2/05