ATMEL AT29LV256-25TC, AT29LV256-25PI, AT29LV256-25PC, AT29LV256-25JI, AT29LV256-25JC Datasheet
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AT29LV256
256K (32K x 8)
3-volt Only
CMOS Flash
Memory
Features
0563A
Single Supply Voltage, Range 3V to 3.6V
•
3-Volt-Only Read and Write Operation
•
Software Protected Program ming
•
Low Power Dissipation
•
15 mA Active Current
20 µA CMOS Standby Curre nt
Fast Read Access Time - 200 ns
•
Sector Program Operatio n
•
Single Cycle Repro gra m (Eras e and Program)
512 Sectors (64 bytes/sec tor)
Internal Address and Data Latches for 64-Bytes
Fast Sector Program Cycl e Ti me - 20 ms Max.
•
Internal Program Control and Timer
•
DATA Polling for End of Program Detec tio n
•
Typical Endurance > 10,000 Cycles
•
CMOS and TTL Compatible Inputs and Outputs
•
Commercial and Industrial Temperature Ranges
•
Description
The AT29LV256 is a 3-volt-only in-system Flash Programmable Erasable Read Only
Memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 200 ns with power dissipation of just 54 mW over the commercial
temperature range. When the device is deselected, the CMOS standby cur rent is less
than 20 µA. The device endurance is such that any sector can typically be written to
in excess of 10,000 times.
(continued)
AT29LV256
Pin Configurations
Pin Name Function
A0 - A14 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
I/O0 - I/O7 Data Inputs/Output s
NC No Connect
DC Don’t Connec t
TSOP Top View
Type 1
PLCC Top View
4-33
Description (Continued)
To allow for simple in-system reprogrammability, the
AT29LV256 does not require high input voltages for programming. Three-volt-only commands determine the operation of the device. Reading data out of the device is
similar to reading from an EPROM. Reprogramming the
AT29LV256 is performed on a sector basis; 64-bytes of
data are loaded into the device and then simultaneously
programmed.
Block Diagram
During a reprogram cycle, the address locations and 64bytes of data are captured at microprocessor speed and
internally latched, freeing the address and data bus for
other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then
program the latched data using an internal control timer.
The end of a program cycle can be detected by
ing of I/O7. Once the end of a program cycle has been
detected, a new access for a read or program can begin.
DATA poll-
Device Operation
READ: The AT29LV256 is accessed like an EPROM.
CE and OE are low and WE is high, the data stored
When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever
line control gives designers flexibility in preventing bus
contention.
SOFTWARE DATA PROTECTION PROGRAMMING:
The AT29LV256 has 512 individual sectors, each 64bytes. Using the software data protection feature, byte
loads are used to enter the 64-bytes of a sector to be programmed. The AT29LV256 can only be programmed or
reprogrammed using the software data protection feature.
The device is programmed on a sector basis. If a byte of
data within the sector is to be changed, data for the entire
64-byte sector must be loaded into the device. The
AT29LV256 automatically does a sector erase prior to
loading the data into the sector. An erase command is not
required.
Software data protection protects the devic e from inadvertent programming. A series of three program commands
to specific addresses with specific data must be presented
to the device before programming may occur. The same
three program commands must begin each program operation. All software program commands must obey the
sector program timing specifications. Power transitions
will not reset the software data protection feature, however
CE or OE is high. This dual-
the softw are feature will guard against i nadvertent pr ogram cycles during power transitions.
Any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data
will be written to the device; however, for the duration of
, a read operation will effectively be a polling operation.
t
WC
After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the
and
CE or WE, whichever occurs last. The data is latched by
the first rising edge of
The 64-bytes of data must be loaded into each sector. Any
byte that is not loaded during the programming of its sector will be erased to read FFh. Once the bytes of a sector
are loaded into the device, they are simultaneously programmed during the internal programming period. After
the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low trans ition
on
WE (or CE) of the preceding byte. If a high to low transition
is not detected within 150 µs of the last low to high transition, the load period will end and the internal programming
period will start. A6 to A14 specify the sector addr ess. The
sector address must be valid during each high to low tran-
WE or CE input with CE or WE low (respectively)
OE high. The address is latched on the falling edge of
CE or WE.
WE (or CE) within 150 µs of the low to high transition of
(continued)
4-34 AT29LV256
Device Operation (Continued)
sition of WE (or CE). A0 to A5 specify the byte address
within the sector. The bytes may be loaded in any order;
sequential loading is not required. Once a programming
operation has been initiated, and for the duration of t
read operation will effectively be a polling operation.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29LV256 in
the following ways: (a) V
(typical), the program function is inhibited. (b) V
on delay— once V
the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit— holding any one
OE low, CE high or WE high inhibits program cycles. (d)
of
Noise filter— pulses of less than 15 ns (typical) on the
CE inputs will not initiate a program cycle.
or
INPUT LEVELS: While operating with a 3.3V ±10%
power supply, the address inputs and control inputs (
CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines
can only be driven from 0 to 3.6 volts.
PRODUCT IDE NTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be us ed by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish
to use the software product identification mode to identify
CC
sense— if VCC is below 1.8V
CC
CC
has reached the VCC sense level,
, a
WC
power
WE
OE,
AT29LV256
the part (i.e. using the device code), and have the system
software use the appropriate sector size for program operations. In th is manner, the user can have a common
board design for 256K to 4-megabit densities and, with
each density’s sector size in a memory map, have the system software apply the appropriate sector size.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT29LV256 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin.
may begin at any time during the program cycle.
TOGGLE BIT: In addition to
AT29LV256 provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE: The entire device
can be erased by using a 6-byte software code. Please
see Software Chip Erase application note for details.
DATA p o l li n g th e
DATA polling
Absolute Maximum Ratings*
Temperature Under Bias.................-55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
Voltage on A9
(including NC Pins)
with Respect to Ground ................... -0.6V to +13.5V
+ 0.6V
CC
*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-
mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
4-35
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