Datasheet AT29LV256-25TC, AT29LV256-25PI, AT29LV256-25PC, AT29LV256-25JI, AT29LV256-25JC Datasheet (ATMEL)

AT29LV256

256K (32K x 8)
3-volt Only
CMOS Flash
Memory

Features

0563A

Single Supply Voltage, Range 3V to 3.6V

•

3-Volt-Only Read and Write Operation

•

Software Protected Program ming

•

Low Power Dissipation

•

15 mA Active Current
20 µA CMOS Standby Curre nt

Fast Read Access Time - 200 ns

•

Sector Program Operatio n

•

Single Cycle Repro gra m (Eras e and Program)
512 Sectors (64 bytes/sec tor)
Internal Address and Data Latches for 64-Bytes

Fast Sector Program Cycl e Ti me - 20 ms Max.

•

Internal Program Control and Timer

•

DATA Polling for End of Program Detec tio n

•

Typical Endurance > 10,000 Cycles

•

CMOS and TTL Compatible Inputs and Outputs

•

Commercial and Industrial Temperature Ranges

•

Description

The AT29LV256 is a 3-volt-only in-system Flash Programmable Erasable Read Only
Memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 200 ns with power dissipation of just 54 mW over the commercial
temperature range. When the device is deselected, the CMOS standby cur rent is less
than 20 µA. The device endurance is such that any sector can typically be written to
in excess of 10,000 times.

(continued)

AT29LV256

Pin Configurations

Pin Name Function

A0 - A14 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
I/O0 - I/O7 Data Inputs/Output s
NC No Connect
DC Don’t Connec t

TSOP Top View

Type 1

PLCC Top View

4-33

Description (Continued)

To allow for simple in-system reprogrammability, the
AT29LV256 does not require high input voltages for pro­gramming. Three-volt-only commands determine the op­eration of the device. Reading data out of the device is
similar to reading from an EPROM. Reprogramming the
AT29LV256 is performed on a sector basis; 64-bytes of
data are loaded into the device and then simultaneously
programmed.

Block Diagram

During a reprogram cycle, the address locations and 64­bytes of data are captured at microprocessor speed and
internally latched, freeing the address and data bus for
other operations. Following the initiation of a program cy­cle, the device will automatically erase the sector and then
program the latched data using an internal control timer.
The end of a program cycle can be detected by
ing of I/O7. Once the end of a program cycle has been
detected, a new access for a read or program can begin.

DATA poll-

Device Operation

READ: The AT29LV256 is accessed like an EPROM.

CE and OE are low and WE is high, the data stored

When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever
line control gives designers flexibility in preventing bus
contention.

SOFTWARE DATA PROTECTION PROGRAMMING:

The AT29LV256 has 512 individual sectors, each 64­bytes. Using the software data protection feature, byte
loads are used to enter the 64-bytes of a sector to be pro­grammed. The AT29LV256 can only be programmed or
reprogrammed using the software data protection feature.
The device is programmed on a sector basis. If a byte of
data within the sector is to be changed, data for the entire
64-byte sector must be loaded into the device. The
AT29LV256 automatically does a sector erase prior to
loading the data into the sector. An erase command is not
required.

Software data protection protects the devic e from inadver­tent programming. A series of three program commands
to specific addresses with specific data must be presented
to the device before programming may occur. The same
three program commands must begin each program op­eration. All software program commands must obey the
sector program timing specifications. Power transitions
will not reset the software data protection feature, however

CE or OE is high. This dual-

the softw are feature will guard against i nadvertent pr o­gram cycles during power transitions.

Any attempt to write to the device without the 3-byte com­mand sequence will start the internal write timers. No data
will be written to the device; however, for the duration of

, a read operation will effectively be a polling operation.

t

WC

After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the
and
CE or WE, whichever occurs last. The data is latched by
the first rising edge of

The 64-bytes of data must be loaded into each sector. Any
byte that is not loaded during the programming of its sec­tor will be erased to read FFh. Once the bytes of a sector
are loaded into the device, they are simultaneously pro­grammed during the internal programming period. After
the first data byte has been loaded into the device, suc­cessive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low trans ition
on
WE (or CE) of the preceding byte. If a high to low transition
is not detected within 150 µs of the last low to high transi­tion, the load period will end and the internal programming
period will start. A6 to A14 specify the sector addr ess. The
sector address must be valid during each high to low tran-

WE or CE input with CE or WE low (respectively)

OE high. The address is latched on the falling edge of

CE or WE.

WE (or CE) within 150 µs of the low to high transition of

(continued)

4-34 AT29LV256

Device Operation (Continued)

sition of WE (or CE). A0 to A5 specify the byte address
within the sector. The bytes may be loaded in any order;
sequential loading is not required. Once a programming
operation has been initiated, and for the duration of t
read operation will effectively be a polling operation.

HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29LV256 in
the following ways: (a) V
(typical), the program function is inhibited. (b) V
on delay— once V
the device will automatically time out 10 ms (typical) be­fore programming. (c) Program inhibit— holding any one

OE low, CE high or WE high inhibits program cycles. (d)

of
Noise filter— pulses of less than 15 ns (typical) on the

CE inputs will not initiate a program cycle.

or
INPUT LEVELS: While operating with a 3.3V ±10%

power supply, the address inputs and control inputs (
CE and WE) may be driven from 0 to 5.5V without ad­versely affecting the operation of the device. The I/O lines
can only be driven from 0 to 3.6 volts.

PRODUCT IDE NTIFICATION: The product identifica­tion mode identifies the device and manufacturer as At­mel. It may be accessed by hardware or software opera­tion. The hardware operation mode can be us ed by an ex­ternal programmer to identify the correct programming al­gorithm for the Atmel product. In addition, users may wish
to use the software product identification mode to identify

CC

sense— if VCC is below 1.8V

CC

CC

has reached the VCC sense level,

, a

WC

power

WE

OE,

AT29LV256

the part (i.e. using the device code), and have the system
software use the appropriate sector size for program op­erations. In th is manner, the user can have a common
board design for 256K to 4-megabit densities and, with
each density’s sector size in a memory map, have the sys­tem software apply the appropriate sector size.

For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING: The AT29LV256 features DATA poll­ing to indicate the end of a program cycle. During a pro­gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin.
may begin at any time during the program cycle.

TOGGLE BIT: In addition to
AT29LV256 provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.

OPTIONAL CHIP ERASE MODE: The entire device
can be erased by using a 6-byte software code. Please
see Software Chip Erase application note for details.

DATA p o l li n g th e

DATA polling

Absolute Maximum Ratings*

Temperature Under Bias.................-55°C to +125°C

Storage Temperature...................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground .............-0.6V to V

Voltage on A9
(including NC Pins)

with Respect to Ground ................... -0.6V to +13.5V

+ 0.6V

CC

*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-

mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi­cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

4-35

DC and AC Operating Range

AT29LV256-15 AT29LV256-20 AT29LV256-25

Operating
Temperature (Case)

V

Power Supply 3.3V ± 0.3V 3.3V ± 0.3V 3.3V ± 0.3V

CC

Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C
Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C

Operating Modes

Mode CE OE WE Ai I/O

Read V
Program

(2)

Standby/Write Inhibit V

IL

V

IL

IH

Program Inhibit X X V
Program Inhibit X V
Output Disable X V
Product Identification

Hardware V

Software

Notes: 1. X can be VIL or VIH.

(5)

2. Refer to AC Programming Waveforms.

= 12.0V ± 0.5V.

3. V

H

IL

V

V

X

V

IL
IH

(1)

IL
IH

IL

V

IH

V

IL

Ai D
Ai D

OUT
IN

X X High Z

IH

X
X High Z

A1 - A14 = VIL, A9 = VH

V

IH

A1 - A14 = VIL, A9 = VH

4. Manufacturer Code: 1F, Device Code: BC.

5. See details unde r Soft ware Product Identif ication Entry/Exit.

A0 = V
A0 = V

A0 = V
A0 = V

IL

IH
IL

IH

(3)

(3)

,

Manufacturer Code

,

Device Code
Manufacturer Code

Device Code

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

CC

V

IL

V

IH

V

OL

V

OH

4-36 AT29LV256

Input Load Current VIN = 0V to V
Output Leakage Current V

VCC Standby Current CMOS CE = V

= 0V to V

I/O

CC

- 0.3V to V

VCC Standby Current TTL CE = 2.0V to V
V

Active Current f = 5 MHz; I

CC

OUT

CC

CC

CC

CC

Com. 20 µA
Ind. 50 µA

= 0 mA; VCC = 3.6V 15 mA

1 µA
1 µA

1mA

Input Low Voltage 0.6 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 1.6 mA; VCC = 3.0V .45 V
Output High Voltage IOH = -100 µA; VCC = 3.0V 2.4 V

AC Read Characteristics

Symbol Parameter

t

ACC

t

CE

t

OE

t

DF

t

OH

(1)
(2)
(3, 4)

Address to Output Delay 150 200 250 ns
CE to Output Delay 150 200 250 ns
OE to Output Delay 0 70 0 100 0 120 ns
CE or OE to Output Float 0 40 0 50 0 60 ns
Output Hold from OE, CE or

Address, whichever occurred first

AT29LV256

AT29LV256-15 AT29LV256-20 AT29LV256-25

Min Max Min Max Min Max

000 ns

Units

AC Read Waveforms

Notes:

1.

CE may be delayed up to t
tion without impact on t
OE may be delayed up to tCE - tOE after the falling edge

2.
of

CE without impact on tCE or by t

change without impact on t

ACC

(1, 2, 3, 4)

- tCE after the address transi-

ACC

.

- tOE after an address

ACC

.

ACC

3. t

DF

(C

L

4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and Me as ur em ent Level

is specified from OE or CE whi chever occurs first

= 5 pF).

Output Test Load

tR, tF < 5 ns

Pin Capacitance

(f = 1 MHz, T = 25°C)

(1)

Typ Max Units Conditions

C

IN

C

OUT

Note: 1. These parameters are characterized an d no t 10 0% tes te d.

46pFV
812pFV

= 0V

IN

= 0V

OUT

4-37

AC Byte Load Characteristics

Symbol Parameter Min Max Units

t

AS

t

AH

t

CS

t

CH

t

WP

t

DS

t

DH

t

WPH

, t

, t

OES

OEH

Address, OE Set-up Time 10 ns
Address Hold Time 100 ns
Chip Select Set-up Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE) 200 ns
Data Set-up Time 100 ns
Data, OE Hold Time 10 ns
Write Pulse Width High 200 ns

AC Byte Load Waveforms

WE Controlled

(1, 2)

CE Controlled

4-38 AT29LV256

AT29LV256

Program Cycle Characteristics

Symbol Parameter Min Max Units

t

WC

t

AS

t

AH

t

DS

t

DH

t

WP

t

BLC

t

WPH

Write Cycle Time 20 ms
Address Set-up Time 10 ns
Address Hold Time 100 ns
Data Set-up Time 100 ns
Data Hold Time 10 ns
Write Pulse Width 200 ns
Byte Load Cycle Time 150 µs
Write Pulse Width High 200 ns

Software Protected Program Waveform

(1, 2, 3)

Notes: 1.

OE must be high when WE and CE are both low.

2. A6 through A14 must specify the sector address
during each high to low transition of
after the software code has been entere d.

Programming Algorithm

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA A0

TO

ADDRESS 5555

LOAD DATA

SECTOR (64 BYTES)

TO

(3)

WE (or CE)

(1)

WRITES ENABLED

ENTER DATA
PROTECT STATE

(2)

3. All bytes that are not load ed within the sector bein g

programmed will be indeterminate.

Notes for software program code:

1. Data Format: I/O7 - I/O0 (Hex );
Address Format: A14 - A0 (Hex).

2. Data Protect sta te will be re-a ct iv at ed at en d of prog ram cyc le .

3. 64-bytes of data MUST BE loaded.

4-39

Data Polling Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

WR

Notes: 1. These parameters are ch ara ct eri ze d an d no t 10 0% tes te d.

2. See t

Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay

(2)

Write Recovery Time 0 ns

spec in AC Read Characteristics.

OE

Data Polling Waveforms

Toggle Bit Characteristic s

(1)

ns

Symbol Parameter Min T yp Max Units

t

DH

t

OEH

t

OE

t

OEHP

t

WR

Notes: 1. These parameters are ch ara ct eri ze d an d no t 10 0% tes te d.

2. See t

Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay

(2)

OE High Pulse 150 ns
Write Recovery Time 0 ns

spec in AC Read Characteristics.

OE

(1, 3)

Toggle Bit Waveforms

Notes: 1. Toggling either OE or CE or both OE and CE will

operate toggle bit.

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address
should not vary.

ns

4-40 AT29LV256

AT29LV256

Software Product

(1)

Identification Entry

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA 90

TO

ADDRESS 5555

PAUSE 20 mS

Notes for software product identification:

1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).

2. A1 - A14 = V
Manufacture Code is read for A0 = V
Device Code is read for A0 = V

3. The device does not remain in identification mode if
powered down.

4. The device returns to st andard operati on mode.

5. Manufacturer Code: 1F
Device Code: BC

.

IL

ENTER PRODUCT
IDENTIFICATION
MODE

;

IL

.

IH

(2, 3, 5)

Software Product
Identification Exit

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA F0

TO

ADDRESS 5555

PAUSE 20 mS

(1)

EXIT PRODUCT
IDENTIFICATION

(4)

MODE

4-41

Ordering Information

t

ACC

(ns)

Active Standby

I

CC

(mA)

Ordering Code Package

Operation Range

150 15 0.02 AT29LV256-15JC 32J Commercial

AT29LV256-15TC 28T (0° to 70°C)

15 0.05 AT29LV256-15JI 32J Industrial

AT29LV256-15TI 28T (-40° to 85°C)

200 15 0.02 AT29LV256-20JC 32J Commercial

AT29LV256-20PC 28P6 (0° to 70°C)
AT29LV256-20TC 28T

15 0.05 AT29LV256-20JI 32J Industrial

AT29LV256-20PI 28P6 (-40° to 85°C)

250 15 0.02 AT29LV256-25JC 32J Commercial

AT29LV256-25PC 28P6 (0° to 70°C)
AT29LV256-25TC 28T

15 0.05 AT29LV256-25JI 32J Industrial

AT29LV256-25PI 28P6 (-40° to 85°C)

Package Type

32J 32 Lead, Plastic J-Leade d Chi p Carrier (PLCC)
28P6 28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28T 28 Lead, Thin Small Outline Package (TSOP)

4-42 AT29LV256