ATMEL AT29LV1024-25TI, AT29LV1024-25TC, AT29LV1024-25JI, AT29LV1024-25JC, AT29LV1024-20TI Datasheet
...
1 Megabit
(64K x 16)
3-volt Only
CMOS Flash
Memory
Features
0564A
Single Voltage, Range 3V to 3.6V Supply
•
3-Volt-Only Read and Write Operation
•
Software Protected Program ming
•
Fast Read Access Time - 150 ns
•
Low Power Dissipation
•
15 mA Active Current
50 µA CMOS Standby Curre nt
Sector Program Operatio n
•
Single Cycle Repro gra m (Eras e and Program)
512 Sectors (128 words/sec tor)
Internal Address and Data Latches for 128 Words
Fast Sector Program Cycl e Ti me - 20 ms
•
Internal Program Control and Timer
•
DATA Polling for End of Program Detec tio n
•
Typical Endurance > 10,000 Cycles
•
CMOS and TTL Compatible Inputs and Outputs
•
Commercial and Industrial Temperature Ranges
•
Description
The AT29LV1024 is a 3-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 1 megabit of memory is organized as 65,536 words by 16
bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 150 ns with power dissipation of just 54 mW. When the device
is deselected, the CMOS standby current is less than 50 µA. The device endurance
is such that any sector can typically be written to in excess of 10,000 times.
To allow for simple in-system reprogrammability, the AT29LV1024 does not require
high input voltages for programming. Three-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an
AT29LV1024
Pin Configurations
Pin Name Function
A0 - A15 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
I/O0 - I/O15
NC No Connect
DC Don’t Connec t
Data
Inputs/Outputs
PLCC Top View
TSOP Top View
Type 1
(continued)
AT29LV1024
4-63
Description (Continued)
EPROM. Reprogramming the AT29LV1024 is performed
on a sector basis; 128 words of data are loaded into the
device and then simultaneously programmed.
During a reprogram cycle, the address locations and 128
words of data are internally latched, freeing the address
and data bus for other operations. Following the initiation
of a program cycle, the device will automatically eras e the
Block Diagram
Device Operation
READ: The AT29LV1024 is accessed like an EPROM.
CE and OE are low and WE is high, the data stored
When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever
line control gives designers flexibility in preventing bus
contention.
SOFTWARE DATA PROTECTION PROGRAMMING:
The AT29LV1024 has 512 individual sectors, each 128
words. Using the software data protection feature, word
loads are used to enter the 128 words of a sector to be
programmed. The AT29LV1024 can only be programmed
or reprogrammed using the software data protection feature. The device is programmed on a sector basis. If a
word of data within the sector is to be changed, data for
the entire 128 word sector must be loaded into the device.
The AT29LV1024 automatically does a sector erase prior
to loading the data into the sector. An erase command is
not required.
Software data protection protects the devic e from inadvertent programming. A series of three program commands
to specific addresses with specific data must be presented
to the device before programming may occur. The same
three program commands must begin each program operation. All software program commands must obey the
sector program timing specifications. Power transitions
will not reset the software data protection feature, however
the softw are feature will guard against i nadvertent program cycles during power transitions.
CE or OE is high. This dual-
sector and then program the latched data using an internal
control timer. The end of a program cycle can be detected
DATA polling of I/O7 or I/O15. Once the end of a pro-
by
gram cycle has been detected, a new access for a read or
program can begin.
Any attempt to write to the device without the 3 word command sequence will start the internal write timers. No data
will be written to the device; however, for the duration of
, a read operation will effectively be a polling operation.
t
WC
After the software data protection’s 3 word command code
is given, a word load is performed by applying a low puls e
on the
and
CE or WE, whichever occurs last. The data is latched by
the first rising edge of
The 128 words of data must be loaded into each sector.
Any word that is not loaded during the programming of its
sector will be erased to read FFFFH. Once the words of a
sector are loaded into the device, they are simultaneously
programmed during the internal programming period. After the first data word has been loaded into the device,
successive words are entered in the same manner. Each
new word to be programmed must have its high to low
transition on
transition of
low transition is not detected within 150 µs of the last low
to high transition, the load period will end and the internal
programming period will start. A7 to A15 specify the sector
address. The sector address must be valid during each
high to low transition of
word address within the sector. The words may be loaded
in any order; sequential loading is not required. Once a
programming operation has been initiated, and for the du-
WE or CE input with CE or WE low (respectively)
OE high. The address is latched on the falling edge of
CE or WE.
WE (or CE) within 150 µs of the low to high
WE (or CE) of the preceding word. If a high to
WE (or CE). A0 to A6 specify the
(continued)
4-64 AT29LV1024
Device Operation (Continued)
ration of tWC, a read operation will effectively be a polling
operation.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29LV1024
in the following ways: (a) V
(typical), the program function is inhibited. (b) V
on delay— once V
the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit— holding any one
OE low, CE high or WE high inhibits program cycles. (d)
of
Noise filter— pulses of less than 15 ns (typical) on the
CE inputs will not initiate a program cycle.
or
INPUT LEVELS: While operating with a 3.3V ±10%
power supply, the address inputs and control inputs (
CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines
can be driven from 0 to 3.6V.
PRODUCT IDE NTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be us ed by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish
to use the software product identification mode to identify
the part (i.e. using the device code), and have the system
software use the appropriate sector size for program operations. In th is manner, the user can have a common
has reached the VCC sense level,
CC
sense— if VCC is below 1.8V
CC
CC
power
WE
OE,
AT29LV1024
board design for various Flash densities and, with each
density’s sector size in a memory map, have the system
software apply the appropriate sector size.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT29LV1024 features DATA
polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last word loaded
will result in the complement of the loaded data on I/O7
and I/O15. Once the program cycle has been completed,
true data is valid on all outputs and the next cycle may
DATA polling may begin at any time during the pro-
begin.
gram cycle.
TOGGLE BIT: In addition to
AT29LV1024 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 and I/O14 toggling between
one and zero. On ce the program cycle has completed,
I/O6 and I/O14 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE: The entire device
can be erased by using a 6-byte software code. Please
see Software Chip Erase application note for details.
DATA p o l li n g th e
Absolute Maximum Ratings*
Temperature Under Bias.................-55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
Voltage on
with Respect to Ground ................... -0.6V to +13.5V
OE
+ 0.6V
CC
*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-
mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
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