Datasheet AT29LV1024-25TI, AT29LV1024-25TC, AT29LV1024-25JI, AT29LV1024-25JC, AT29LV1024-20TI Datasheet (ATMEL)

1 Megabit
(64K x 16)
3-volt Only
CMOS Flash
Memory

Features

0564A

Single Voltage, Range 3V to 3.6V Supply

•

3-Volt-Only Read and Write Operation

•

Software Protected Program ming

•

Fast Read Access Time - 150 ns

•

Low Power Dissipation

•

15 mA Active Current
50 µA CMOS Standby Curre nt

Sector Program Operatio n

•

Single Cycle Repro gra m (Eras e and Program)
512 Sectors (128 words/sec tor)
Internal Address and Data Latches for 128 Words

Fast Sector Program Cycl e Ti me - 20 ms

•

Internal Program Control and Timer

•

DATA Polling for End of Program Detec tio n

•

Typical Endurance > 10,000 Cycles

•

CMOS and TTL Compatible Inputs and Outputs

•

Commercial and Industrial Temperature Ranges

•

Description

The AT29LV1024 is a 3-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 1 megabit of memory is organized as 65,536 words by 16
bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 150 ns with power dissipation of just 54 mW. When the device
is deselected, the CMOS standby current is less than 50 µA. The device endurance
is such that any sector can typically be written to in excess of 10,000 times.

To allow for simple in-system reprogrammability, the AT29LV1024 does not require
high input voltages for programming. Three-volt-only commands determine the opera­tion of the device. Reading data out of the device is similar to reading from an

AT29LV1024

Pin Configurations

Pin Name Function

A0 - A15 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable

I/O0 - I/O15
NC No Connect

DC Don’t Connec t

Data
Inputs/Outputs

PLCC Top View

TSOP Top View

Type 1

(continued)

AT29LV1024

4-63

Description (Continued)

EPROM. Reprogramming the AT29LV1024 is performed
on a sector basis; 128 words of data are loaded into the
device and then simultaneously programmed.

During a reprogram cycle, the address locations and 128
words of data are internally latched, freeing the address
and data bus for other operations. Following the initiation
of a program cycle, the device will automatically eras e the

Block Diagram

Device Operation

READ: The AT29LV1024 is accessed like an EPROM.

CE and OE are low and WE is high, the data stored

When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever
line control gives designers flexibility in preventing bus
contention.

SOFTWARE DATA PROTECTION PROGRAMMING:

The AT29LV1024 has 512 individual sectors, each 128
words. Using the software data protection feature, word
loads are used to enter the 128 words of a sector to be
programmed. The AT29LV1024 can only be programmed
or reprogrammed using the software data protection fea­ture. The device is programmed on a sector basis. If a
word of data within the sector is to be changed, data for
the entire 128 word sector must be loaded into the device.
The AT29LV1024 automatically does a sector erase prior
to loading the data into the sector. An erase command is
not required.

Software data protection protects the devic e from inadver­tent programming. A series of three program commands
to specific addresses with specific data must be presented
to the device before programming may occur. The same
three program commands must begin each program op­eration. All software program commands must obey the
sector program timing specifications. Power transitions
will not reset the software data protection feature, however
the softw are feature will guard against i nadvertent pro­gram cycles during power transitions.

CE or OE is high. This dual-

sector and then program the latched data using an internal
control timer. The end of a program cycle can be detected

DATA polling of I/O7 or I/O15. Once the end of a pro-

by
gram cycle has been detected, a new access for a read or
program can begin.

Any attempt to write to the device without the 3 word com­mand sequence will start the internal write timers. No data
will be written to the device; however, for the duration of

, a read operation will effectively be a polling operation.

t

WC

After the software data protection’s 3 word command code
is given, a word load is performed by applying a low puls e
on the
and
CE or WE, whichever occurs last. The data is latched by
the first rising edge of

The 128 words of data must be loaded into each sector.
Any word that is not loaded during the programming of its
sector will be erased to read FFFFH. Once the words of a
sector are loaded into the device, they are simultaneously
programmed during the internal programming period. Af­ter the first data word has been loaded into the device,
successive words are entered in the same manner. Each
new word to be programmed must have its high to low
transition on
transition of
low transition is not detected within 150 µs of the last low
to high transition, the load period will end and the internal
programming period will start. A7 to A15 specify the sector
address. The sector address must be valid during each
high to low transition of
word address within the sector. The words may be loaded
in any order; sequential loading is not required. Once a
programming operation has been initiated, and for the du-

WE or CE input with CE or WE low (respectively)

OE high. The address is latched on the falling edge of

CE or WE.

WE (or CE) within 150 µs of the low to high

WE (or CE) of the preceding word. If a high to

WE (or CE). A0 to A6 specify the

(continued)

4-64 AT29LV1024

Device Operation (Continued)

ration of tWC, a read operation will effectively be a polling
operation.

HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29LV1024
in the following ways: (a) V
(typical), the program function is inhibited. (b) V
on delay— once V
the device will automatically time out 10 ms (typical) be­fore programming. (c) Program inhibit— holding any one

OE low, CE high or WE high inhibits program cycles. (d)

of
Noise filter— pulses of less than 15 ns (typical) on the

CE inputs will not initiate a program cycle.

or
INPUT LEVELS: While operating with a 3.3V ±10%

power supply, the address inputs and control inputs (
CE and WE) may be driven from 0 to 5.5V without ad­versely affecting the operation of the device. The I/O lines
can be driven from 0 to 3.6V.

PRODUCT IDE NTIFICATION: The product identifica­tion mode identifies the device and manufacturer as At­mel. It may be accessed by hardware or software opera­tion. The hardware operation mode can be us ed by an ex­ternal programmer to identify the correct programming al­gorithm for the Atmel product. In addition, users may wish
to use the software product identification mode to identify
the part (i.e. using the device code), and have the system
software use the appropriate sector size for program op­erations. In th is manner, the user can have a common

has reached the VCC sense level,

CC

sense— if VCC is below 1.8V

CC

CC

power

WE

OE,

AT29LV1024

board design for various Flash densities and, with each
density’s sector size in a memory map, have the system
software apply the appropriate sector size.

For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING: The AT29LV1024 features DATA
polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last word loaded
will result in the complement of the loaded data on I/O7
and I/O15. Once the program cycle has been completed,
true data is valid on all outputs and the next cycle may

DATA polling may begin at any time during the pro-

begin.
gram cycle.

TOGGLE BIT: In addition to
AT29LV1024 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 and I/O14 toggling between
one and zero. On ce the program cycle has completed,
I/O6 and I/O14 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time dur­ing a program cycle.

OPTIONAL CHIP ERASE MODE: The entire device
can be erased by using a 6-byte software code. Please
see Software Chip Erase application note for details.

DATA p o l li n g th e

Absolute Maximum Ratings*

Temperature Under Bias.................-55°C to +125°C

Storage Temperature...................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground .............-0.6V to V

Voltage on

with Respect to Ground ................... -0.6V to +13.5V

OE

+ 0.6V

CC

*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-

mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi­cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

4-65

DC and AC Operating Range

AT29LV1024-15 AT29LV1024-20 AT29LV1024-25

Operating
Temperature (Case)

V

Power Supply

CC

1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an operational
mode is started.

(1)

Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C
Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C

3.3V ± 0.3V 3.3V ± 0.3V 3.3V ± 0.3V

Operating Modes

Mode CE OE WE Ai I/O

Read V
Program

(2)

Standby/Write Inhibit V

IL

V

IL

IH

Program Inhibit X X V
Program Inhibit X V
Output Disable X V
Product Identification

Hardware V

Software

Notes: 1. X can be VIL or VIH.

(5)

2. Refer to AC Programming Waveforms.

3. V

= 12.0V ± 0.5V.

H

IL

V

V

X

V

IL
IH

(1)

IL
IH

IL

V

IH

V

IL

X X High Z

IH

X
X High Z

A1 - A15 = VIL, A9 = VH,

V

IH

A1 - A15 = VIL, A9 = VH,

4. Manufacturer Code: 1F, Device Code: 26

5. See details under So ft ware Produ ct Ide nt if ic at io n Ent ry/Exit.

Ai D
Ai D

(3)

A0 = V

A0 = V

A0 = V

A0 = V

IL

IH
IL

IH

(3)

OUT
IN

Manufacturer Code
Device Code

(4)

Manufacturer Code
Device Code

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

CC

V

IL

V

IH

V

OL

V

OH1

Input Load Current VIN = 0V to V
Output Leakage Current V

VCC Standby Current CMOS CE = V

= 0V to V

I/O

CC

- 0.3V to V

VCC Standby Current TTL CE = 2.0V to V
V

Active Current f = 5 MHz; I

CC

OUT

CC

CC

CC

= 0 mA, V

CC

Com. 50 µA
Ind. 100 µA

= 3.6V 15 mA

CC

1 µA
1 µA

1mA

Input Low Voltage 0.6 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 1.6 mA, VCC = 3.0V .45 V
Output High Voltage IOH = 100 µA, VCC = 3.0V 2.4 V

4-66 AT29LV1024

AC Read Characteristics

Symbol Parameter

t

ACC

t

CE

t

OE

t

DF

t

OH

(1)
(2)
(3, 4)

Address to Output Delay 150 200 250 ns
CE to Output Delay 150 200 250 ns
OE to Output Delay 0 85 0 100 0 120 ns
CE or OE to Output Float 0 40 0 50 0 60 ns
Output Hold from OE, CE or

Address, whichever occurred first

AT29LV1024

AT29LV1024-15 AT29LV1024-20 AT29LV1024-25

Min Max Min Max Min Max

000ns

Units

AC Read Waveforms

Notes: 1. CE may be delayed up to t

transition without impact on t
OE may be delayed up to tCE - tOE after the falling

2.
edge of
after an address change without impact on t

CE without impact on tCE or by t

(1, 2, 3, 4)

- tCE after the address

ACC

.

ACC

ACC

- tOE

ACC

3. t

DF

(C

L

4. This parameter is characterized and is not 100% tested.

.

Input Test Waveforms and Me as ur em ent Level

is specified from OE or CE whichever occurs fir st

= 5 pF).

Output Test Load

tR, tF < 5 ns

Pin Capacitance

(f = 1 MHz, T = 25°C)

(1)

Typ Max Units Conditions

C

IN

C

OUT

Note: 1. This parameter is characterized and is not 100% tested.

46pFV
812pFV

= 0V

IN

= 0V

OUT

4-67

AC Word Load Characteristics

Symbol Parameter Min Max Units

t

AS

t

AH

t

CS

t

CH

t

WP

t

DS

t

DH

t

WPH

, t

, t

OES

OEH

Address, OE Set-up Time 0 ns
Address Hold Time 100 ns
Chip Select Set-up Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE) 200 ns
Data Set-up Time 100 ns
Data, OE Hold Time 0 ns
Write Pulse Width High 200 ns

AC Word Load Waveforms

WE Controlled

(1, 2)

CE Controlled

Notes: 1. The software data protection commands must be

applied prior to word loads.

4-68 AT29LV1024

2. A complete sector (128 words) should be loaded using
these waveforms as shown in the Soft ware Prote ct ed
Word Load waveforms (see nex t page).

2. OE must be high when WE and CE are both low.

3. All words that are not lo ad ed within the sector being

programmed will be indeterminate.

AT29LV1024

Program Cycle Characteristics

Symbol Parameter Min Max Units

t

WC

t

AS

t

AH

t

DS

t

DH

t

WP

t

WLC

t

WPH

Write Cycle Time 20 ms
Address Set-up Time 0 ns
Address Hold Time 100 ns
Data Set-up Time 100 ns
Data Hold Time 0 ns
Write Pulse Width 200 ns
Word Load Cycle Time 150 µs
Write Pulse Width High 200 ns

Software Protected P r ogr am Wav ef orm

(1, 2, 3)

Notes: 1. A7 through A15 must specify the same page

address during each high to low transition of WE

CE) after the software code ha s be en ent ere d.

(or

(1)

Programming Algorithm

LOAD DATA AAAA

TO

ADDRESS 5555

LOAD DATA 5555

TO

ADDRESS 2AAA

LOAD DATA A0A0

TO

ADDRESS 5555

LOAD DATA

TO

SECTOR (128 WORDS)

WRITES ENABLED

(3)

ENTER DATA
PROTECT STATE

(2)

Notes for software program code:

1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).

2. Data Protect state will be re-a ct iv at ed at en d of program cycle.

3. 128 words of data MUST BE loaded.

4-69

Data Polling Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

WR

Notes: 1. These parameters are ch ara ct erized and not 100% tes te d.

2. See t

Data Hold Time 0 ns
OE Hold Time 0 ns
OE to Output Delay

(2)

Write Recovery Time 0 ns

spec in AC Read Characteristics.

OE

Data Polling Waveforms

Toggle Bit Characteristic s

(1)

ns

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

OEHP

t

WR

Notes: 1. These parameters are ch ara ct erized and not 100% tes te d.

2. See t

Toggle Bit Waveforms

Notes: 1. Toggling either

operate toggle bit.

2. Beginning and ending state of I/O6 and I/O14
may vary.

Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay

(2)

OE High Pulse 150 ns
Write Recovery Time 0 ns

spec in AC Read Characteristics.

OE

(1, 2, 3)

OE or CE or both OE and CE will

3. Any address location may be used but the address
should not vary.

ns

4-70 AT29LV1024

AT29LV1024

Software Product

(1)

Identification Entry

LOAD DATA AAAA

TO

ADDRESS 5555

LOAD DATA 5555

TO

ADDRESS 2AAA

LOAD DATA 9090

TO

ADDRESS 5555

PAUSE 20 mS

Notes for software product identification:

1. Data Format: I/O15 - I/O0 (Hex );
Address Format: A14 - A0 (Hex).

2. A1 - A15 = V
Manufacture Code is read for A0 = V
Device Code is read for A0 = V

3. The device doe s no t remai n in ide nt ification mode if
powered down.

4. The device returns to st an dard operation mode.

5. Manufacturer Code: 1F
Device Code: 26

.

IL

ENTER PRODUCT
IDENTIFICATION
MODE

;

IL

.

IH

(2, 3, 5)

Software Product
Identification Exit

LOAD DATA AAAA

TO

ADDRESS 5555

LOAD DATA 5555

TO

ADDRESS 2AAA

LOAD DATA F0F0

TO

ADDRESS 5555

PAUSE 20 mS

(1)

EXIT PRODUCT
IDENTIFICATION

(4)

MODE

4-71

Ordering Information

t

ACC

(ns)

Active Standby

I

CC

(mA)

Ordering Code Package

Operation Range

150 15 0.05 AT29LV1024-15JC 44J Commercial

AT29LV1024-15TC 48T (0° to 70°C)

15 0.05 AT29LV1024-15JI 44J Industrial

AT29LV1024-15TI 48T (-40° to 85°C)

200 15 0.05 AT29LV1024-20JC 44J Commercial

AT29LV1024-20TC 48T (0° to 70°C)

15 0.10 AT29LV1024-20JI 44J Industrial

AT29LV1024-20TI 48T (-40° to 85°C)

250 15 0.05 AT29LV1024-25JC 44J Commercial

AT29LV1024-25TC 48T (0° to 70°C)

15 0.10 AT29LV1024-25JI 44J Industrial

AT29LV1024-25TI 48T (-40° to 85°C)

Package Type

44J 44 Lead, Plastic J-Leade d Chip Carrier (PLCC)
48T 48 Lead, Thin Small Outline Package (TSOP)

4-72 AT29LV1024