ATMEL AT29C256-12TC, AT29C256-12PI, AT29C256-12PC, AT29C256-12JI, AT29C256-12JC Datasheet

256K (32K x 8)
5-volt Only
CMOS Flash
Memory

Features

0046L

Fast Read Access Time - 70 ns

•

5-Volt-Only Reprogramming

•

Page Program Operatio n

•

Single Cycle Repro gra m (Eras e and Program)
Internal Address and Data Latches for 64-Bytes

Internal Program Control and Timer

•

Hardware and Software Data Protection

•

Fast Program Cycle Ti me s

•

Page (64-Byte) Program Ti me - 10 ms
Chip Erase Time - 10 ms

DATA Polling for End of Program Detec tio n

•

Low Power Dissipation

•

50 mA Active Current
300 µA CMOS Standby Current

Typical Endurance > 10,000 Cycles

•

Single 5V ± 10% Supply

•

CMOS and TTL Compatible Inputs and Outputs

•

Commercial and Industrial Temperature Ranges

•

Description

The AT29C256 is a 5-volt-only in-s ystem Flash programmable and eras able read only
memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits. Manu­factured with Atmel’s advanced nonvolatile CMOS technology, the device offers ac­cess times to 70 ns with power dissipation of just 275 mW. When the device is dese­lected, the CMOS standby current is less than 300 µA. The device endurance is such
that any sector can typically be written to in excess of 10,000 times.

(continued)

Pin Configurations

Pin Name Function

A0 - A14 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect

DIP Top View

PLCC Top View

AT29C256

AT29C256

Note: PLCC package pins 1 and 17
are DON’T CONNECT.

TSOP Top View

Type 1

4-93

Description (Continued)

To allow for simple in-system reprogrammability, the
AT29C256 does not require high input voltages for pro­gramming. Five-volt-only commands determine the opera­tion of the device. Reading data out of the device is similar
to reading from a static RAM. Reprogramming the
AT29C256 is performed on a page basis; 64-bytes of data
are loaded into the device and then simultaneously pro­grammed. The contents of the entire device may be
erased by using a 6-byte software code (although erasure
before programming is not needed).

Block Diagram

Device Operation

READ: The AT29C256 is accessed like a static RAM.

CE and OE are low and WE is high, the data stored

When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever
line control gives designers flexibility in preventing bus
contention.

BYTE LOAD: A byte load is performed by applying a
low pulse on the
spectively) and
falling edge of
is latched by the first rising edge of
are used to enter the 64-bytes of a page to be pro­grammed or the software codes for data protection and
chip erasure.

PROGRAM: The device is reprogrammed on a page
basis. If a byte of data within a page is to be changed, data
for the entire page must be loaded into the device. Any
byte that is not loaded during the programming of its page
will be indeterminate. Once the bytes of a page are loaded
into the device, they are simultaneously programmed dur­ing the internal programming period. After the first data
byte has been loaded into the device, successive bytes
are entered in the same manner. Each new byte to be pro­grammed must have its high to low transition on
CE) within 150 µs of the low to high transition of WE (or
CE) of the preceding byte. If a high to low transition is not
detected within 150 µs of the last low to high transition, the

WE or CE input with CE or WE low (re-

OE high. The address is latched on the

CE or WE, whichever occurs last. The data

CE or OE is high. This dual-

CE or WE. Byte loads

WE (or

During a reprogram cycle, the address locations and 64­bytes of data are internally latched, freeing the address
and data bus for other operations. Following the initiation
of a program cycle, the device will automatically erase the
page and then program the latched data using an internal
control timer. The end of a program cycle can be detected

DATA polling of I/O7. Once the end of a program cycle

by
has been detected a new access for a read, program or
chip erase can begin.

load period will end and the internal programming period
will start. A6 to A14 specify the page address. The page
address must be valid during each high to low transition of
WE (or CE). A0 to A5 specify the byte address within the
page. The bytes may be loaded in any order; sequential
loading is not required. Once a programming operation
has been initiated, and for the duration of t
eration will effectively be a polling operation.

SOFTWARE DATA PROTECTION: A software control­led data protection feature is available on the AT29C256.
Once the software protection is enabled a software algo­rithm must be issued to the device before a program may
be performed. The software protection feature may be en­abled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable
the software data protection, a series of three program
commands to specific addresses with specific data must
be performed. After the software data protection is en­abled the sa me three program com mands must begin
each program cycle in order for the programs to occur. Al l
software program commands must obey the page pro­gram timing specifications. Once set, the software data
protection feature remains active unless its disable com­mand is issued. Power transitions will not reset the soft­ware data protection feature, however the software fea­ture will guard against inadvertent program cycles during
power transitions.

, a read op-

WC

(continued)

4-94 AT29C256

Device Operation (Continued)

Once set, software data protection will remain active un­less the disable command sequence is issued.

After setting SDP, any attempt to write to the device with­out the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of t
a polling operation.

After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the
and
CE or WE, whichever occurs last. The data is latched by
the first rising edge of
must be loaded into each sector by the same procedure as
outlined in the program section under device operation.

HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29C256 in
the following ways: (a) V
(typical), the program function is inhibited. (b) V
on delay— once V
the device will automatically time out 5 ms (typical) before
programming. (c) Program inhibit— holding any one of
low,

WE or CE input with CE or WE low (respectively)

OE high. The address is latched on the falling edge of

CE high or WE high inhibits program cycles. (d) Noise

, a read operation will effectively be

WC

CE or WE. The 64-bytes of data

sense— if VCC is below 3.8V

CC

CC

has reached the VCC sense level,

CC

power

OE

AT29C256

filter— pulses of less than 15 ns (typical) on the
inputs will not initiate a program cycle.

PRODUCT IDE NTIFICATION: The product identifica­tion mode identifies the device and manufacturer and may
be accessed by a hardware operation. For details, see
Operating Modes or Product Identification.

DATA POLLING: The AT29C256 features DATA poll­ing to indicate the end of a program cycle. During a pro­gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin.
may begin at any time during the program cycle.

TOGGLE BIT: In addition to
AT29C256 provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.

OPTIONAL CHIP ERASE MODE: The entire device
can be erased by using a 6-byte software code. Please
see Software Chip Erase application note for details.

DATA p o l li n g th e

WE or CE

DATA polling

Absolute Maximum Ratings*

Temperature Under Bias.................-55°C to +125°C

Storage Temperature...................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground .............-0.6V to V

Voltage on OE

with Respect to Ground ................... -0.6V to +13.5V

+ 0.6V

CC

*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-

mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi­cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

4-95

DC and AC Operating Range

AT29C256-70 AT29C256-90 AT29C256-12 AT29C256-15

Operating
Temperature (Case)

V

Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10%

CC

Com. 0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C
Ind. -40°C - 85°C -40°C - 85°C-40°C - 85°C -40°C - 85°C

Operating Modes

Mode CE OE WE Ai I/O

Read V
Program

(2)

5V Chip Erase V
Standby/Write Inhibit V

IL

V

IL
IL

IH

Write Inhibit X X V
Write Inhibit X V
Output Disable X V
High Voltage Chip Erase V

IL

Product Identification

Hardware V

Software

Notes: 1. X can be VIL or VIH.

(5)

2. Refer to AC Programming Waveforms.

= 12.0V ± 0.5V.

3. V

H

IL

V

IL

V

IH

V

IH

(1)

X

IL

IH

VH

V

IL

(3)

V

IH

V

IL

V

IL

Ai D
Ai D
Ai

OUT
IN

X X High Z

IH

X
X High Z

VIL X High Z

A1 - A14 = VIL, A9 = VH,

V

IH

4. Manufacturer Code: 1F, Device Code: DC

5. See details unde r Soft ware Product Identific at io n Ent ry/ Exit.

A1 - A14 = VIL, A9 = VH,

A0 = V
A0 = V

A0 = V
A0 = V

IL

IH
IL

IH

Manufacturer Code
Device Code

Manufacturer Code
Device Code

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

CC

V

IL

V

IH

V

OL

V

OH1

V

OH2

4-96 AT29C256

Input Load Current VIN = 0V to V
Output Leakage Current V

= 0V to V

I/O

CC

CC

VCC Standby Current CMOS CE = VCC - 0.3V to V
VCC Standby Current TTL CE = 2.0V to V
V

Active Current f = 5 MHz; I

CC

CC

= 0 mA 50 mA

OUT

CC

10 µA
10 µA

300 µA

3mA

Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA .45 V
Output High Voltage IOH = -400 µA 2.4 V
Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V