ATMEL AT29C1024 User Manual

1 Megabit
(64K x 16)
5-volt Only
CMOS Flash
Memory

0571A

查询AT29C1024供应商

Features

Fast Read Access Time - 70 ns

•

5-Volt-Only Reprogramming

•

Sector Program Operatio n

•

Single Cycle Repro gra m (Eras e and Program)
512 Sectors (128 words/sec tor)
Internal Address and Data Latches for 128 Words

Internal Program Control and Timer

•

Hardware and Software Data Protection

•

Fast Sector Program Cycl e Ti me - 10 ms

•

DATA Polling for End of Program Detec tio n

•

Low Power Dissipation

•

60 mA Active Current
200 µA CMOS Standby Current

Typical Endurance > 10,000 Cycles

•

Single 5V ±10% Sup pl y

•

CMOS and TTL Compatible Inputs and Outputs

•

Commercial and Industrial Temperature Ranges

•

Description

The AT29C1024 is a 5-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 1 megabit of memory is organized as 65,536 words by 16
bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 70 ns with power dissipation of just 330 mW. When the device
is deselected, the CMOS standby current is less than 200 µA. The device endurance
is such that any sector can typically be written to in excess of 10,000 times.

AT29C1024

Pin Configurations

Pin Name Function

A0 - A15 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable

I/O0 - I/O15
NC No Connect

DC Don’t Connec t

Data
Inputs/Outputs

PLCC Top View

(continued)

AT29C1024

TSOP Top View

Type 1

4-141

Description (Continued)

To allow for simple in-system reprogrammability, the
AT29C1024 does not require high input voltages for pro­gramming. Five-volt-only commands determine the opera­tion of the device. Reading data out of the device is similar
to reading from an EPROM. Reprogramming the
AT29C1024 is performed on a sector basis; 128 words of
data are loaded into the device and then simultaneously
programmed.

Block Diagram

Device Operation

READ: The AT29C1024 is accessed like an EPROM.

CE and OE are low and WE is high, the data stored

When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever
line control gives designers flexibility in preventing bus
contention.

DATA LOAD: Data loads are used to enter the 128
words of a sector to be programmed or the software codes
for data protection. A data load is performed by applying a
low pulse on the
spectively) and
falling edge of
is latched by the first rising edge of

PROGRAM: The device is reprogrammed on a sector
basis. If a word of data within a sector is to be changed,
data for the entire sector must be loaded into the device.
Any word that is not loaded during the programming of its
sector will be erased to read FFH. Once the words of a
sector are loaded into the device, they are simultaneously
programmed during the internal programming period. Af­ter the first data word has been loaded into the device,
successive words are entered in the same manner. Each
new word to be programmed must have its high to low
transition on
transition of
low transition is not detected within 150 µs of the last low
to high transition, the load period will end and the internal
programming period will start. A7 to A15 specify the sector

WE or CE input with CE or WE low (re-

OE high. The address is latched on the

CE or WE, whichever occurs last. The data

WE (or CE) within 150 µs of the low to high

WE (or CE) of the preceding word. If a high to

CE or OE is high. This dual-

CE or WE.

During a reprogram cycle, the address locations and 128
words of data are internally latched, freeing the address
and data bus for other operations. Following the initiation
of a program cycle, the device will automatically eras e the
sector and then program the latched data using an internal
control timer. The end of a program cycle can be detected

DATA polling of I/O7 or I/O15. Once the end of a pro-

by
gram cycle has been detected, a new access for a read or
program can begin.

address. The sector address must be valid during each
high to low transition of
word address within the sector. The words may be loaded
in any order; sequential loading is not required. Once a
programming operation has been initiated, and for the du­ration of t
operation.

SOFTWARE DATA PROTECTION: A software control­led data protection feature is available on the AT29C1024.
Once the software protection is enabled a software algo­rithm must be issued to the device before a program may
be performed. The software protection feature may be en­abled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable
the software data protection, a series of three program
commands to specific addresses with specific data must
be performed. After the software data protection is en­abled the sa me three program com mands must begin
each program cycle in order for the programs to occur. Al l
software program commands must obey the sector pro­gram timing specifications. Once set, software data pro­tection will remain active unless the disable command se­quence is issued. Power transitions will not reset the soft­ware data protection feature, however the software fea­ture will guard against inadvertent program cycles during
power transitions.

, a read operation will effectively be a polling

WC

WE (or CE). A0 to A6 specify the

(continued)

4-142 AT29C1024

Device Operation (Continued)

After setting SDP, any attempt to write to the device with­out the 3-word command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of t
a polling operation.

After the software data protection’s 3-word command
code is given, a sector of data is loaded into the device
using the sector programming timing specifications.

HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29C1024 in
the following ways: (a) V
(typical), the program function is inhibited. (b) V
on delay— once V
the device will automatically time out 5 ms (typical) before
programming. (c) Program inhibit— holding any one of

CE high or WE high inhibits program cycles. (d) Noise

low,
filter— pulses of less than 15 ns (typical) on the
inputs will not initiate a program cycle.

PRODUCT IDE NTIFICATION: The product identifica­tion mode identifies the device and manufacturer as At­mel. It may be accessed by hardware or software opera­tion. The hardware operation mode can be us ed by an ex­ternal programmer to identify the correct programming al­gorithm for the Atmel product. In addition, users may wish
to use the software product identification mode to identify
the part (i.e. using the device code), and have the system
software use the appropriate sector size for program op-

, a read operation will effectively be

WC

sense— if VCC is below 3.8V

CC

CC

has reached the VCC sense level,

CC

WE or CE

power

OE

AT29C1024

erations. In th is manner, the user can have a common
board design for various Flash densities and, with each
density’s sector size in a memory map, have the system
software apply the appropriate sector size.

For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING: The AT29C1024 features DATA poll­ing to indicate the end of a program cycle. During a pro­gram cycle an attempted read of the last word loaded will
result in the complement of the loaded data on I/O7 and
I/O15. Once the program cycle has been completed, true
data is valid on all outputs and the next cycle may begin.
DATA polling may begin at any time during the program
cycle.

TOGGLE BIT: In addition to
AT29C1024 provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 and I/O14 toggling between
one and zero. On ce the program cycle has completed,
I/O6 and I/O14 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time dur­ing a program cycle.

OPTIONAL CHIP ERASE MODE: The entire device
can be erased by using a 6-byte software code. Please
see Software Chip Erase application note for details.

DATA p o l li n g th e

Absolute Maximum Ratings*

Temperature Under Bias.................-55°C to +125°C

Storage Temperature...................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground .............-0.6V to V

Voltage on

with Respect to Ground ................... -0.6V to +13.5V

OE

+ 0.6V

CC

*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-

mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi­cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

4-143

DC and AC Operating Range

AT29C1024-70 AT29C1024-90 AT29C1024-12 AT29C1024-15

Operating
Temperature (Case)

V

Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10%

CC

Com. 0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C
Ind. -40°C - 85°C-40°C - 85°C-40°C - 85°C-40°C - 85°C

Operating Modes

Mode CE OE WE Ai I/O

Read V
Program

(2)

5V Chip Erase V
Standby/Write Inhibit V

IL

V

IL
IL

IH

Program Inhibit X X V
Program Inhibit X V
Output Disable X V
Product Identification

Hardware V

Software

Notes: 1. X can be VIL or VIH.

(5)

2. Refer to AC Programming Waveforms.

= 12.0V ± 0.5V.

3. V

H

IL

V
V
V

X

V

IL
IH
IH

(1)

IL
IH

IL

V

IH

V

IL

V

IL

X X High Z

IH

X
X High Z

A1 - A15 = VIL, A9 = VH,

V

IH

A1 - A15 = VIL, A9 = VH,

4. Manufacturer Code: 1F, Device Code: 25

5. See details unde r Soft ware Product Identif ic at io n Ent ry/ Exit.

Ai D
Ai D
Ai

(3)

A0 = V

A0 = V
A0 = V

A0 = V

IL

IH
IL

IH

(3)

OUT
IN

Manufacturer Code
Device Code

Manufacturer Code
Device Code

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

CC

V

IL

V

IH

V

OL

V

OH1

V

OH2

4-144 AT29C1024

Input Load Current VIN = 0V to V
Output Leakage Current V

VCC Standby Current CMOS CE = V

= 0V to V

I/O

CC

- 0.3V to V

VCC Standby Current TTL CE = 2.0V to V
V

Active Current f = 5 MHz; I

CC

OUT

CC

CC

CC

CC

Com. 200 µA
Ind. 200 µA

= 0 mA 60 mA

10 µA
10 µA

3mA

Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA .45 V
Output High Voltage IOH = -400 µA 2.4 V
Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V