ATMEL AT29C040A-15TC, AT29C040A-15PI, AT29C040A-15PC, AT29C040A-12TI, AT29C040A-12TC Datasheet

Features

Fast Read Access Time - 100 ns

•

5-Volt-Only Reprogramming

•

Sector Program Operation

•

Single Cycle Reprogra m (Er as e an d Prog r am)
2048 Sectors (256 bytes/sector)
Internal Address and Data Latches for 256-Bytes

Internal Program Control and Timer

•

Hardware and Software Data Protection

•

Two 16 KB Boot Blocks with Lockout

•

Fast Sector Program Cycle Time - 10 ms

•

DATA Polling for End of Program Detection

•

Low Power Dissipation

•

40 mA Active Current
100 µA CMOS Standby Current

Typical Endurance > 10,000 Cycles

•

Single 5V ± 10% Supply

•

CMOS and TTL Compatible Inputs and Outputs

•

Description

The AT29C040A is a 5-volt-only in-system Flash Programmable and Erasable Read
Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology,
the device offers access times up to 100 ns, and a low 220 mW power dissipation.
When the device is deselected, the CMO S standby cur rent is less than 100 µA. The
device endurance is such that any sector can typically be written to in excess of
10,000 times. The programming algorithm is compatible with other devices in Atmel’s
5-volt-only Flash family.

(continued)

4-Megabit
(512K x 8)
5-volt Only
256-Byte Sector
CMOS Flash
Memory

AT29C040A

Pin Configurations

Pin Name Function

A0 - A18 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect

TSOP Top View

Type 1

AT29C040A

DIP Top View

0333E–9/97

Description

To allow for simple in-system reprogrammability, the
AT29C040A does not require high input voltages for pro­gramming. Five-volt-only commands determine the opera­tion of the device. Reading data out of the device is similar
to reading from an EPROM. Reprogramming the
AT29C040A is performed on a sector basis; 256-bytes of
data are loaded into the device and then simultaneously
programmed.

(Continued)

Block Diagram

Device Operation

READ:

When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever
line control gives designers flexibility in preventing bus
contention.

BYTE LOAD:

bytes of a sector to be programmed or the software codes
for data protection. A byte load is performed by applying a
low pulse on the
spectively) and
falling edge of
is latched by the first rising edge of

PROGRAM:

basis. If a byte of data within a sector is to be changed,
data for the entire sector must be loaded into the device.
Any byte that is not loaded during the programming of its
sector will be erased to read FFH. Once the bytes of a
sector are loaded into the device, they are simultaneously
programmed during the internal programming period. Af­ter the first data byte has been loaded into the device, suc­cessive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low transition
on
WE (or CE) of the preceding byte. If a high to low transition
is not detected within 150 µs of the last low to high transi­tion, the load period will end and the internal programming
period will start. A8 to A18 specify the sector address. The
sector address must be valid during each high to low tran-

The AT29C040A is accessed like an EPROM.

CE and OE are low and WE is high, the data stored

CE or OE is high. This dual-

B yte loads are used to enter the 256-

WE or CE input with CE or WE low (re-

OE high. The address is latched on the

CE or WE, whichever occurs last. The data

CE or WE.

The device is reprogrammed on a sector

WE (or CE) within 150 µs of the low to high transition of

During a reprogram cycle, the address locations and 256­bytes of data are internally latched, freeing the address
and data bus for other operations. Following the initiation
of a program cycle, the device will automatically erase the
sector and then program the latched data using an internal
control timer. The end of a program cycle can be detected

DATA polling of I/O7. Once the end of a program cycle

by
has been detected, a new access for a read or program
can begin.

sition of
within the sector. The bytes may be loaded in any order;
sequential loading is not required. Once a programming
operation has been initiated, and for the duration of t
read operation will effectively be a polling operation.

SOFTWARE DATA PROTECTION:

led data protection feature is available on the AT29C040A.
Once the software protection is enabled a software algo­rithm must be issued to the device before a program may
be performed. The software protection feature may be en­abled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable
the softwa re data protection, a series of three program
commands to specific addresses with specific data must
be performed. After the software data protection is en­abled the sa me three program com mands must begin
each program cycle in order for the programs to occur. All
software program commands must obey the sector pro­gram timing specifications. The SDP feature protects all
sectors, not just a single sector. Once set, the software
data protection feature remains active unless its disable
command is issued. Power transitions will not reset the
software data protection feature, however the software
feature will guard against inadvertent program cycles dur­ing power transitions.

After setting SDP, any attempt to write to the device with­out the three-byte command sequence will start the inter­nal write timers. No data will be written to the device; how­ever, for the duration of t
tively be a polling operation.

WE (or CE). A0 to A7 specify the byte address

, a

WC

A software control-

, a read operation will effec-

WC

(continued)

2

AT29C040A

AT29C040A

Device Operation

After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the
and
CE or WE, whichever occurs last. The data is latched by
the first rising edge of
must be loaded into each sector by the same procedure as
outlined in the program section under device operation.

HARDWARE DATA PROTECTION:

protect against inadvertent programs to the AT29C040A
in the following ways: (a) V
(typical), the program function is inhibited. (b) V
on delay— once V
the device will automatically time out 5 ms (typical) before
programming. (c) Program inhibit— holding any one of
low,
filter— pulses of less than 15 ns (typical) on the
inputs will not initiate a program cycle.

PRODUCT IDENTIFICATION:

tion mode identifies the device and manufacturer as At­mel. It may be accessed by hardware or software opera­tion. The hardware operation mode can be used by an ex­ternal programmer to identify the correct programming al­gorithm for the Atmel product. In addition, users may wish
to use the software product identification mode to identify
the part (i.e. using the device code), and have the system
software use the appropriate sector size for program op­erations. I n this manner, the u ser can have a common
board design for 256K to 4-megabit densities and, with
each density’s sector size in a memory map, have the sys­tem software apply the appropriate sector size.

For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING:

ing to indicate the end of a program cycle. During a pro­gram cycle an attempted read of the last byte loaded will

WE or CE input with CE or WE low (respectively)

OE high. The address is latched on the falling edge of

CC

CE high or WE high inhibits program cycles. (d) Noise

The AT29C040A features

(Continued)

CE or WE. The 256-bytes of data

Hardware features

sense— if VCC is below 3.8V

CC

power

CC

has reached the VCC sense level,

OE

WE or CE

The product identifica-

DATA poll-

Absolute Maximum Ratings*

Temperature Under Bias.................-55°C to +125°C

Storage Temperature......................-65°C to +150°C

result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin.
may begin at any time during the program cycle.

TOGGLE BIT:

AT29C040A provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 tog gling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.

OPTIONAL CHIP ERASE MODE:

can be erased by using a 6-byte software code. P lease
see Software Chip Erase application note for details.

BOOT BLOCK PROGRAMMING LOCKOUT:

AT29C040A has two designated memory blocks that have
a programming lockout feature. This feature prevents pro­gramming of data in the designated block once the feature
has been enabled. Each of these blocks consists of 16K
bytes; the programming lockout feature can be set inde­pendently for either block. While the lockout feature does
not have to be activated, it can be activated for either or
both blocks.

These two 16K memory sections are referred to as

. Secure code which will bring up a system can be

blocks

contained in a boot block. The AT29C040A blocks are lo­cated in the first 16K bytes of memory and the last 16K
bytes of memory. The boot block programming lockout
feature can therefore support systems that boot from the
lower addresses of memory or the higher addresses.
Once the programming lockout feature has been acti­vated, the data in that block can no longer be erased or
programmed; data in other memory locations can still be
changed through the regular programming methods. To
activate the lockout feature, a series of seven program
commands to specific addresses with specific data must
be performed. Please see Boot Block Lockout Feature En­able Algorithm.

If the boot block lockout featu re has been activated on
either block, the chip erase function will be disabled.

In addition to

DATA polling the

The entire device

DATA polling

The

boot

(continued)

All Input Voltages
(including NC Pins)

with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground .............-0.6V to V

Voltage on OE

with Respect to Ground ................... -0.6V to +13.5V

+ 0.6V

CC

*NOTICE: Stresses beyond those listed under “A bsolute Maxi-

mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or an y ot he r con ditions beyond tho se ind i­cated in the oper ational secti ons of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

3

Device Operation

BOOT BLOCK LOCKOUT DETECTION:

method is available to determine whether programming of
either boot block section is locked out. See Software Prod­uct Identification Entry and Exit sections. When the device
is in the software product identification mode, a read from
location 00002H will show if programming the lower ad-

(Continued)

A software

FFFF2H will do so for the upper boot block. If the data is
FE, the corresponding block can be programmed; if the
data is FF, the program lockout feature has been activated
and the corresponding block cannot be programmed. The
software product identification exit mode should be used
to return to standard operation.

dress boot block is locked out wh ile reading location

DC and AC Operating Range

AT29C040A-10 AT29C040A-12 AT29C040A-15

Operating
Temperature (Case)

V

Power Supply 5V ± 10% 5V ± 10% 5V ± 10%

CC

Com. 0°C - 70°C0°C - 70°C0°C - 70°C
Ind. -40°C - 85°C-40°C - 85°C-40°C - 85°C

Operating Modes

Mode

Read V
Program

(2)

Standby/Write Inhibit V
Program Inhibit X X V
Program Inhibit X V
Output Disable X V

CE OE WE

IL

V

IL

IH

V

V

X

IL
IH

(1)

IL
IH

V

IH

V

X X High Z

IH

X
X High Z

Ai I/O

Ai D

IL

Ai D

OUT
IN

Product Identification

(3)

Manufacturer Code

(3)

Device Code
Manufacturer Code

Device Code

(4)

(4)

Hardware V

Software

Notes: 1. X can be VIL or VIH.

(5)

2. Refer to AC Programming Waveforms.

3. VH = 12.0V ± 0.5V.

A1 - A18 = VIL, A9 = VH,

IL

V

IL

V

IH

A1 - A18 = VIL, A9 = VH,

4. Manufacturer Code: 1F, Device Code: A4

5. See details unde r Soft ware Produ ct Ide nt if icat io n Ent ry/ Exit.

A0 = V
A0 = V

A0 = V
A0 = V

IL

IH
IL

IH

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

CC

V

IL

V

IH

V

OL

V

OH1

V

OH2

Input Load Current VIN = 0V to V
Output Leakage Current V

VCC Standby Current CMOS CE = V

= 0V to V

I/O

CC

- 0.3V to V

VCC Standby Current TTL CE = 2.0V to V
V

Active Current f = 5 MHz; I

CC

OUT

CC

CC

CC

CC

Com. 100 µA
Ind. 300 µA

= 0 mA 40 mA

10 µA
10 µA

3mA

Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA .45 V
Output High Voltage IOH = -400 µA2.4V
Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

(4)

(4)

4

AT29C040A