BDTIC www.BDTIC.com/ATMEL
Features
• Fast Read Access Time – 90 ns
• 5-volt Only Reprogramming
• Sector Program Operation
– Single Cycle Reprogram (Erase and Program)
– 2048 Sectors (256 Bytes/Sector)
– Internal Address and Data Latches for 256 Bytes
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Two 16K Bytes Boot Blocks with Lockout
• Fast Sector Program Cycle Time – 10 ms
• DATA Polling for End of Program Detection
• Low Power Dissipation
– 40 mA Active Current
– 100 µA CMOS Standby Current
• Typical Endurance > 10,000 Cycles
• Single 5V ± 10% Supply
• Green (Pb/Halide-free) Packaging Option
4-megabit
(512K x 8)
5-volt Only
256-byte Sector
Flash Memory
1. Description
The AT29C040A is a 5-volt only in-system Flash Programmable and Erasable Read
Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology,
the device offers access times up to 90 ns, and a low 220 mW power dissipation.
When the device is deselected, the CMOS standby current is less than 100 µA. The
device endurance is such that any sector can typically be written to in excess of
10,000 times. The programming algorithm is compatible with other devices in Atmel’s
5-volt only Flash family.
To allow for simple in-system reprogrammability, the AT29C040A does not require
high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an
EPROM. Reprogramming the AT29C040A is performed on a sector basis; 256 bytes
of data are loaded into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 256 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation
of a program cycle, the device will automatically erase the sector and then program
the latched data using an internal control timer. The end of a program cycle can be
detected by DATA
detected, a new access for a read or program can begin.
polling of I/O7. Once the end of a program cycle has been
AT29C040A
0333L–FLASH–9/08
2. Pin Configurations
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
4
3
2
1
323130
14151617181920
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
A12
A15
A16
A18
VCCWEA17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Pin Name Function
A0 - A18 Addresses
CE Chip Enable
OE
WE
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
2.1 32-lead PLCC Top View
Output Enable
Write Enable
2.2 32-lead TSOP Top View – Type 1
2
AT29C040A
0333L–FLASH–9/08
3. Block Diagram
4. Device Operation
4.1 Read
The AT29C040A is accessed like an EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state whenever CE
trol gives designers flexibility in preventing bus contention.
AT29C040A
or OE is high. This dual-line con-
4.2 Byte Load
Byte loads are used to enter the 256 bytes of a sector to be programmed or the software codes
for data protection. A byte load is performed by applying a low pulse on the WE
CE
or WE low (respectively) and OE high. The address is latched on the falling edge of CE or
WE
, whichever occurs last. The data is latched by the first rising edge of CE or WE.
4.3 Program
The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed,
data for the entire sector must be loaded into the device. Any byte that is not loaded during the
programming of its sector will be erased to read FFH. Once the bytes of a sector are loaded into
the device, they are simultaneously programmed during the internal programming period. After
the first data byte has been loaded into the device, successive bytes are entered in the same
manner. Each new byte to be programmed must have its high to low transition on WE
within 150 μs of the low to high transition of WE
transition is not detected within 150 μs of the last low to high transition, the load period will end
and the internal programming period will start. A8 to A18 specify the sector address. The sector
address must be valid during each high to low transition of WE
address within the sector. The bytes may be loaded in any order; sequential loading is not
required. Once a programming operation has been initiated, and for the duration of t
operation will effectively be a polling operation.
4.4 Software Data Protection
A software controlled data protection feature is available on the AT29C040A. Once the software
protection is enabled a software algorithm must be issued to the device before a program may
or CE input with
(or CE)
(or CE) of the preceding byte. If a high to low
(or CE). A0 to A7 specify the byte
, a read
WC
0333L–FLASH–9/08
3
be performed. The software protection feature may be enabled or disabled by the user; when
shipped from Atmel, the software data protection feature is disabled. To enable the software
data protection, a series of three program commands to specific addresses with specific data
must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program
commands must obey the sector program timing specifications. The SDP feature protects all
sectors, not just a single sector. Once set, the software data protection feature remains active
unless its disable command is issued. Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during
power transitions.
After setting SDP, any attempt to write to the device without the three-byte command sequence
will start the internal write timers. No data will be written to the device; however, for the duration
of t
, a read operation will effectively be a polling operation.
WC
After the software data protection’s 3-byte command code is given, a byte load is performed by
applying a low pulse on the WE
address is latched on the falling edge of CE
the first rising edge of CE
same procedure as outlined in the program section under device operation.
4.5 Hardware Data Protection
Hardware features protect against inadvertent programs to the AT29C040A in the following
ways: (a) V
power on delay – once VCC has reached the VCC sense level, the device will automatically time
out 5 ms (typical) before programming; (c) Program inhibit – holding any one of OE
or WE
the WE
CC
high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on
or CE inputs will not initiate a program cycle.
or CE input with CE or WE low (respectively) and OE high. The
or WE, whichever occurs last. The data is latched by
or WE. The 256 bytes of data must be loaded into each sector by the
sense – if VCC is below 3.8V (typical), the program function is inhibited; (b) V
low, CE high
CC
4.6 Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product. In
addition, users may wish to use the software product identification mode to identify the part
(i.e. using the device code), and have the system software use the appropriate sector size for
program operations. In this manner, the user can have a common board design for 256K to
4-megabit densities and, with each density’s sector size in a memory map, have the system software apply the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
4.7 DATA Polling
The AT29C040A features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded
data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and
the next cycle may begin. DATA
4.8 Toggle Bit
In addition to DATA polling the AT29C040A provides another method for determining the end of
a program or erase cycle. During a program or erase operation, successive attempts to read
polling may begin at any time during the program cycle.
4
AT29C040A
0333L–FLASH–9/08
data from the device will result in I/O6 toggling between one and zero. Once the program cycle
has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may
begin at any time during a program cycle.
4.9 Optional Chip Erase Mode
The entire device can be erased by using a 6-byte software code. Please see Software Chip
Erase application note for details.
4.10 Boot Block Programming Lockout
The AT29C040A has two designated memory blocks that have a programming lockout feature.
This feature prevents programming of data in the designated block once the feature has been
enabled. Each of these blocks consists of 16K bytes; the programming lockout feature can be
set independently for either block. While the lockout feature does not have to be activated, it can
be activated for either or both blocks.
These two 16K memory sections are referred to as boot blocks. Secure code which will bring up
a system can be contained in a boot block. The AT29C040A blocks are located in the first 16K
bytes of memory and the last 16K bytes of memory. The boot block programming lockout feature
can therefore support systems that boot from the lower addresses of memory or the higher
addresses. Once the programming lockout feature has been activated, the data in that block can
no longer be erased or programmed; data in other memory locations can still be changed
through the regular programming methods. To activate the lockout feature, a series of seven
program commands to specific addresses with specific data must be performed. Please see
Boot Block Lockout Feature Enable Algorithm.
AT29C040A
If the boot block lockout feature has been activated on either block, the chip erase function will
be disabled.
4.10.1 Boot Block Lockout Detection
A software method is available to determine whether programming of either boot block section is
locked out. See Software Product Identification Entry and Exit sections. When the device is in
the software product identification mode, a read from location 00002H will show if programming
the lower address boot block is locked out while reading location 7FFF2H will do so for the upper
boot block. If the data is FE, the corresponding block can be programmed; if the data is FF, the
program lockout feature has been activated and the corresponding block cannot be programmed. The software product identification exit mode should be used to return to standard
operation.
5. Absolute Maximum Ratings*
Temperature Under Bias............................... -55° C to +125°C
Storage Temperature .................................... -65°C to +150° C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
+ 0.6V
CC
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
0333L–FLASH–9/08
5
6. DC and AC Operating Range
AT29C040A-90 AT29C040A-12
Operating Temperature (Case) Industrial -40° C - 85° C-40° C - 85° C
VCC Power Supply 5V ± 10% 5V ± 10%
7. Operating Modes
Mode CE OE WE Ai I/O
X
V
IL
V
IH
(1)
Read V
Program
(2)
Standby/Write Inhibit V
IL
V
IL
IH
Program Inhibit X X V
Program Inhibit X V
Output Disable X V
IL
IH
Product Identification
Hardware V
Software
(5)
IL
V
IL
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
= 12.0V ± 0.5V.
3. V
H
4. Manufacturer Code: 1F, Device Code: A4.
5. See details under Software Product Identification Entry/Exit.
V
IH
V
IL
Ai D
Ai D
X X High Z
IH
X
X High Z
V
IH
A1 - A18 = VIL, A9 = VH,
A0 = V
A0 = V
A1 - A18 = VIL, A9 = VH,
(3)
A0 = V
(3)
A0 = V
IL
IH
Manufacturer Code
IL
IH
Device Code
Manufacturer Code
Device Code
OUT
IN
(4)
(4)
(4)
(4)
8. DC Characteristics
Symbol Parameter Condition Min Max Units
I
LI
I
LO
I
SB1
I
SB2
I
CC
V
IL
V
IH
V
OL
V
OH1
V
OH2
6
Input Load Current VIN = 0V to V
Output Leakage Current V
= 0V to V
I/O
VCC Standby Current CMOS CE = V
VCC Standby Current TTL CE = 2.0V to V
V
Active Current f = 5 MHz; I
CC
- 0.3V to V
CC
OUT
CC
CC
CC
CC
= 0 mA 40 mA
Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA 0.45 V
Output High Voltage IOH = -400 µA 2.4 V
Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V
AT29C040A
10 µA
10 µA
300 µA
3mA
0333L–FLASH–9/08
9. AC Read Characteristics
Symbol Parameter
AT29C040A
AT29C040A-90 AT29C040A-12
UnitsMin Max Min Max
t
t
t
t
t
ACC
CE
OE
DF
OH
(1)
(2)
(3)(4)
Address to Output Delay 90 120 ns
CE to Output Delay 90 120 ns
OE to Output Delay 0 40 0 50 ns
CE or OE to Output Float 0 25 0 30 ns
Output Hold from OE, CE or Address, whichever
occurred first
10. AC Read Waveforms
00ns
(1)(2)(3)(4)
Notes: 1. CE may be delayed up to t
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by t
without impact on t
is specified from OE or CE whichever occurs first (CL = 5 pF).
3. t
DF
ACC
.
4. This parameter is characterized and is not 100% tested.
0333L–FLASH–9/08
- tCE after the address transition without impact on t
ACC
ACC
.
- tOE after an address change
ACC
7
11. Input Test Waveforms and Measurement Level
tR, tF < 5 ns
12. Output Test Load
13. Pin Capacitance
f = 1 MHz, T = 25°C
Symbol Typ Max Units Conditions
(1)
C
IN
C
OUT
Note: 1. This parameter is characterized and is not 100% tested.
46pFV
812pFV
IN
OUT
= 0V
= 0V
8
AT29C040A
0333L–FLASH–9/08
AT29C040A
14. AC Byte Load Characteristics
Symbol Parameter Min Max Units
t
AS
t
AH
t
CS
t
CH
t
WP
t
DS
t
DH
t
WPH
, t
OES
, t
OEH
Address, OE Setup Time 10 ns
Address Hold Time 50 ns
Chip Select Setup Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE)90ns
Data Setup Time 50 ns
Data, OE Hold Time 10 ns
Write Pulse Width High 100 ns
15. AC Byte Load Waveforms
15.1 WE Controlled
15.2 CE Controlled
(1)
Note: 1. A complete sector (256 bytes) should be loaded using the waveforms shown in these byte load waveform diagrams.
0333L–FLASH–9/08
9
16. Program Cycle Characteristics
Symbol Parameter Min Max Units
t
WC
t
AS
t
AH
t
DS
t
DH
t
WP
t
BLC
t
WPH
Write Cycle Time 10 ms
Address Setup Time 10 ns
Address Hold Time 50 ns
Data Setup Time 50 ns
Data Hold Time 10 ns
Write Pulse Width 90 ns
Byte Load Cycle Time 150 µs
Write Pulse Width High 100 ns
17. Program Cycle Waveforms
(1)(2)(3)
Notes: 1. A8 through A18 must specify the sector address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.
10
AT29C040A
0333L–FLASH–9/08
AT29C040A
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA
TO
SECTOR (256 BYTES)
(4)
WRITES ENABLED
ENTER DATA
PROTECT STATE
(2)
18. Software Data Protection
Enable Algorithm
(1)
19. Software Data Protection
Disable Algorithm
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
(1)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
20. Software Protected Program Cycle Waveform
Notes: 1. A8 through A18 must specify the sector address during each high to low transition of WE (or CE) after the software code has
0333L–FLASH–9/08
LOAD DATA 20
TO
ADDRESS 5555
Address Format: A14 - A0 (Hex).
2. Data Protect state will be activated at end of program
cycle.
3. Data Protect state will be deactivated at end of
program period.
LOAD DATA
TO
SECTOR (256 BYTES)
4. 256 bytes of data MUST BE loaded.
(1)(2)(3)
been entered.
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.
EXIT DATA
PROTECT STATE
(4)
(3)
11
21. Data Polling Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
t
t
t
DH
OEH
OE
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See t
spec in AC Read Characteristics.
OE
22. Data Polling Waveforms
ns
23. Toggle Bit Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
OEHP
t
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
OE High Pulse 150 ns
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See t
24. Toggle Bit Waveforms
spec in AC Read Characteristics.
OE
(1)(2)(3)
ns
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The t
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
12
AT29C040A
specification must be met by the toggling
OEHP
0333L–FLASH–9/08
AT29C040A
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
PAUSE 10 mS ENTER PRODUCT
IDENTIFICATION
MODE
(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 10 mS EXIT PRODUCT
IDENTIFICATION
MODE
(4)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA 00
TO
ADDRESS 00000H
(2)
PAUSE 10 mS
LOAD DATA FF
TO
ADDRESS 7FFFFH
(3)
PAUSE 10 mS
25. Software Product Identification
Entry
(1)
26. Software Product Identification
(1)
Exit
27. Boot Block Lockout
Feature Enable Algorithm
(1)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A18 = V
Manufacturer Code is read for A0 = V
Device Code is read for A0 = VIH.
.
IL
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is A4.
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Lockout feature set on lower address boot block.
3. Lockout feature set on higher address boot block.
;
IL
0333L–FLASH–9/08
13
28. Ordering Information
28.1 Green Package Option (Pb/Halide-free)
I
t
ACC
(ns)
90
120
(mA)
CC
40 0.3
40 0.3
Ordering Code Package Operation RangeActive Standby
AT29C040A-90JU
AT29C040A-90TU
AT29C040A-12JU
AT29C040A-12TU
32J
32T
32J
32T
Industrial
(-40° to 85° C)
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32T 32-lead, Thin Small Outline Package (TSOP)
14
AT29C040A
Package Type
0333L–FLASH–9/08
29. Packaging Information
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
R
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
B
32J
10/04/01
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1
E2
B
e
E1 E
D1
D
D2
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2 9.906 – 10.922
E 14.859 – 15.113
E1 13.894 – 14.046 Note 2
E2 12.471 – 13.487
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
29.1 32J – PLCC
AT29C040A
0333L–FLASH–9/08
15
29.2 32T – TSOP Type 1
2325 Orchard Parkway
San Jose, CA 95131
TITLE
DRAWING NO.
R
REV.
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
B
32T
10/18/01
PIN 1
D1
D
Pin 1 Identifier
b
e
E
A
A1
A2
0º ~ 8º
c
L
GAGE PLANE
SEATING PLANE
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
16
AT29C040A
0333L–FLASH–9/08
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