ATMEL AT29C040A User Manual

BDTIC www.BDTIC.com/ATMEL

Features

• Fast Read Access Time – 90 ns

• 5-volt Only Reprogramming

• Sector Program Operation

– Single Cycle Reprogram (Erase and Program) – 2048 Sectors (256 Bytes/Sector) – Internal Address and Data Latches for 256 Bytes

• Internal Program Control and Timer

• Hardware and Software Data Protection

• Two 16K Bytes Boot Blocks with Lockout

• Fast Sector Program Cycle Time – 10 ms

• DATA Polling for End of Program Detection

• Low Power Dissipation

– 40 mA Active Current – 100 µA CMOS Standby Current

• Typical Endurance > 10,000 Cycles

• Single 5V ± 10% Supply

• Green (Pb/Halide-free) Packaging Option

4-megabit (512K x 8) 5-volt Only 256-byte Sector Flash Memory

1. Description

The AT29C040A is a 5-volt only in-system Flash Programmable and Erasable Read Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology, the device offers access times up to 90 ns, and a low 220 mW power dissipation. When the device is deselected, the CMOS standby current is less than 100 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times. The programming algorithm is compatible with other devices in Atmel’s 5-volt only Flash family.

To allow for simple in-system reprogrammability, the AT29C040A does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C040A is performed on a sector basis; 256 bytes of data are loaded into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 256 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA detected, a new access for a read or program can begin.

polling of I/O7. Once the end of a program cycle has been

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2. Pin Configurations

5 6 7 8 9 10 11 12 13

29 28 27 26 25 24 23 22 21

A7 A6 A5 A4 A3 A2 A1 A0

I/O0

A14 A13 A8 A9 A11 OE A10 CE I/O7

323130

14151617181920

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

A12

A15

A16

A18

VCCWEA17

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

A11

A8 A13 A14 A17

VCC

A18 A16 A15 A12

OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3

Pin Name Function

A0 - A18 Addresses

CE Chip Enable

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

2.1 32-lead PLCC Top View

Output Enable

Write Enable

2.2 32-lead TSOP Top View – Type 1

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3. Block Diagram

4. Device Operation

4.1 Read

The AT29C040A is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE trol gives designers flexibility in preventing bus contention.

AT29C040A

or OE is high. This dual-line con-

4.2 Byte Load

Byte loads are used to enter the 256 bytes of a sector to be programmed or the software codes for data protection. A byte load is performed by applying a low pulse on the WE CE

or WE low (respectively) and OE high. The address is latched on the falling edge of CE or

, whichever occurs last. The data is latched by the first rising edge of CE or WE.

4.3 Program

The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any byte that is not loaded during the programming of its sector will be erased to read FFH. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high to low transition on WE within 150 μs of the low to high transition of WE transition is not detected within 150 μs of the last low to high transition, the load period will end and the internal programming period will start. A8 to A18 specify the sector address. The sector address must be valid during each high to low transition of WE address within the sector. The bytes may be loaded in any order; sequential loading is not required. Once a programming operation has been initiated, and for the duration of t operation will effectively be a polling operation.

4.4 Software Data Protection

A software controlled data protection feature is available on the AT29C040A. Once the software protection is enabled a software algorithm must be issued to the device before a program may

or CE input with

(or CE)

(or CE) of the preceding byte. If a high to low

(or CE). A0 to A7 specify the byte

, a read

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be performed. The software protection feature may be enabled or disabled by the user; when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the sector program timing specifications. The SDP feature protects all sectors, not just a single sector. Once set, the software data protection feature remains active unless its disable command is issued. Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions.

After setting SDP, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of t

, a read operation will effectively be a polling operation.

After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE address is latched on the falling edge of CE the first rising edge of CE same procedure as outlined in the program section under device operation.

4.5 Hardware Data Protection

Hardware features protect against inadvertent programs to the AT29C040A in the following ways: (a) V power on delay – once VCC has reached the VCC sense level, the device will automatically time out 5 ms (typical) before programming; (c) Program inhibit – holding any one of OE or WE the WE

high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on

or CE inputs will not initiate a program cycle.

or CE input with CE or WE low (respectively) and OE high. The

or WE, whichever occurs last. The data is latched by

or WE. The 256 bytes of data must be loaded into each sector by the

sense – if VCC is below 3.8V (typical), the program function is inhibited; (b) V

low, CE high

4.6 Product Identification

The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish to use the software product identification mode to identify the part (i.e. using the device code), and have the system software use the appropriate sector size for program operations. In this manner, the user can have a common board design for 256K to 4-megabit densities and, with each density’s sector size in a memory map, have the system software apply the appropriate sector size.

For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.

4.7 DATA Polling

The AT29C040A features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA

4.8 Toggle Bit

In addition to DATA polling the AT29C040A provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read

polling may begin at any time during the program cycle.

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data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

4.9 Optional Chip Erase Mode

The entire device can be erased by using a 6-byte software code. Please see Software Chip Erase application note for details.

4.10 Boot Block Programming Lockout

The AT29C040A has two designated memory blocks that have a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. Each of these blocks consists of 16K bytes; the programming lockout feature can be set independently for either block. While the lockout feature does not have to be activated, it can be activated for either or both blocks.

These two 16K memory sections are referred to as boot blocks. Secure code which will bring up a system can be contained in a boot block. The AT29C040A blocks are located in the first 16K bytes of memory and the last 16K bytes of memory. The boot block programming lockout feature can therefore support systems that boot from the lower addresses of memory or the higher addresses. Once the programming lockout feature has been activated, the data in that block can no longer be erased or programmed; data in other memory locations can still be changed through the regular programming methods. To activate the lockout feature, a series of seven program commands to specific addresses with specific data must be performed. Please see Boot Block Lockout Feature Enable Algorithm.

AT29C040A

If the boot block lockout feature has been activated on either block, the chip erase function will be disabled.

4.10.1 Boot Block Lockout Detection

A software method is available to determine whether programming of either boot block section is locked out. See Software Product Identification Entry and Exit sections. When the device is in the software product identification mode, a read from location 00002H will show if programming the lower address boot block is locked out while reading location 7FFF2H will do so for the upper boot block. If the data is FE, the corresponding block can be programmed; if the data is FF, the program lockout feature has been activated and the corresponding block cannot be programmed. The software product identification exit mode should be used to return to standard operation.

5. Absolute Maximum Ratings*

Temperature Under Bias............................... -55° C to +125°C

Storage Temperature .................................... -65°C to +150° C

All Input Voltages (including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

+ 0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Voltage on OE

with Respect to Ground ...................................-0.6V to +13.5V

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