ATMEL AT29C020-10JI, AT29C020-10JC, AT29C020-15JC, AT29C020-12TI, AT29C020-12TC Datasheet
...
Features
µ
µ
Fast Read Access Time - 90 ns
•
5-Volt-Only Reprogramming
•
Sector Program Operation
•
Single Cycle Reprogra m (Er as e an d Prog r am)
1024 Sectors (256 bytes/sector)
Internal Address and Data Latches for 256-Bytes
Internal Program Control and Timer
•
Hardware and Software Data Protection
•
Two 8 KB Boot Blocks with Lockout
•
Fast Sector Program Cycle Time - 10 ms
•
DATA Polling for End of Program Detection
•
Low Power Dissipation
•
40 mA Active Current
A CMOS Standby Current
100
Typical Endurance > 10,000 Cycles
•
Single 5V ±10% Supply
•
CMOS and TTL Compatible Inputs and Outputs
•
Commercial and Industrial Temperature Ranges
•
Description
The AT29C020 is a 5-volt-only in-system Flash programmable and erasable read only
memory (PEROM). Its 2 megabits of memory is organized as 262,144 bytes. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the dev ice offers access times to 90 ns with power diss ipation of jus t 220 mW over the c ommercial temperature range. When the device is deselected, the CMOS standby current is less
than 100
excess of 10,000 times.
A. Device endurance is such that any sector can typically be written to in
(continued)
2-Megabit
(256K x 8)
5-volt Only
CMOS Flash
Memory
AT29C020
Pin Configurations
Pin Name Function
A0 - A17 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
PLCC Top View
DIP Top View
TSOP Top View
Type 1
AT29C020
0291I/G20-I–6/97
Description
µ
To allow for simple in-system reprogrammability, the
AT29C020 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar
to reading from an EPROM. Reprogramming the
AT29C020 is performed on a sector basis; 256-bytes of
data are loaded into the device and then simultaneously
programmed.
(Continued)
Block Diagram
Device Operation
READ:
When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever
line control gives designers flexibility in preventing bus
contention.
BYTE LOAD:
bytes of a sector to be programmed or the software codes
for data protection. A byte load is performed by applying a
low pulse on the
spectively) and
falling edge of
is latched by the first rising edge of
PROGRAM:
basis. If a byte of data within a sector is to be changed,
data for the entire sector must be loaded into the device.
Any byte that is not loaded during the programming of its
sector will be indeterminate. Once the bytes of a sector
are loaded into the device, they ar e simultaneously programmed during the internal programming period. After
the first data byte has been loaded into the device, suc cessive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low transition
on
WE (or CE) of the preceding byte. If a high to low transition
is not detected within 150
tion, the load period will end and the internal programming
Th e AT29C020 is accesse d like an EPROM.
CE and OE are low and WE is high, the data stored
CE or OE is high. This dual-
B yte loads are used to enter the 256-
WE or CE input with CE or WE low (re-
OE high. The address is latched on the
CE or WE, whichever occurs last. The data
CE or WE.
The device is reprogrammed on a sector
WE (or CE) within 150 µs of the low to high transition of
s of the last low to high transi-
During a reprogram cycle, the address locations and 256bytes of data are internally latched, freeing the address
and data bus for other operations. Following the initiation
of a program cycle, the device will automatically erase the
sector and then program the latched data using an internal
control timer. The end of a program cycle can be detected
DATA polling of I/O7. Once the end of a program cycle
by
has been detected, a new access for a read or program
can begin.
period will start. A8 to A17 specify the sector address. The
sector address must be valid during each high to low transition of
within the sector. The bytes may be loaded in any order;
sequential loading is not required. Once a programming
operation has been initiated, and for the duration of t
read operation will effectively be a polling operation.
SOFTWARE DATA PROTECTION:
led data protection feature is available on the AT29C020.
Once the software protection is enabled a software algorithm must be issued to the device before a program may
be performed. The software protection feature may be enabled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable
the softwa re data protection, a s eries of three program
commands to specific addresses with specific data must
be performed. After the software data protection is enabled the sa me three program com mands must begin
each program cycle in order for the programs to occur. All
software program commands must obey the sector program timing specifications. Once set, the software data
protection feature remains active unless its disable command is issued. Power transitions will not reset the so ftware data protection feature, however the software feature will guard against inadvertent program cycles during
power transitions.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal
WE (or CE). A0 to A7 specify the byte address
, a
WC
A software control-
(continued)
2
AT29C020
AT29C020
Device Operation
write timers. No data will be written to the device; however,
for the duration of t
a polling operation.
After the software data protection’s 3-byte command code
is given, a sector of data is loaded into the device using the
sector program timing specifications.
HARDWARE DATA PROTECTION:
protect against inadvertent programs to the AT29C020 in
the following ways: (a) V
(typical), the program function is inhibited. (b) V
on delay— once V
the device will automatically time out 5 ms (typical) before
programming. (c) Program inhibit— holding any one of
CE high or WE high inhibits program cycles. (d) Noise
low,
filter— pulses of less than 15 ns (typical) on the
inputs will not initiate a program cycle.
PRODUCT IDENTIFICATION:
tion mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish
to use the software product identification mode to identify
the part (i.e. using the device code), and have the system
software use the appropriate sector size for program operations. I n this manner, the u ser can have a common
board design for 256K to 4-megabit densities and, with
each density’s sector size in a memory map, have the system software apply the appropriate sector size.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING:
ing to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
WC
CC
The AT29C020 features
(Continued)
, a read operation will effectively be
Hardware features
sense— if VCC is below 3.8V
CC
power
CC
has reached the VCC sense level,
OE
WE or CE
The product identifica-
DATA poll-
Absolute Maximum Ratings*
Temperature Under Bias.................-55°C to +125°C
Storage Temperature......................-65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
+ 0.6V
CC
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin.
may begin at any time during the program cycle.
TOGGLE BIT:
AT29C020 provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 tog gling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE:
can be erased by using a 6-byte software code. P lease
see Software Chip Erase application note for details.
BOOT BLOCK PROGRAMMING LOCKOUT:
AT29C020 has two designated memory blocks that have
a programming lockout feature. This feature prevents programming of data in the designated block once the feature
has been enabled. Each of these blocks consists of 8K
bytes; the programming lockout feature can be set independently for either block. While the lockout feature does
not have to be activated, it can be activated for either or
both blocks.
These two 8K memory sections are referred to as
. Secure code which will bring up a system can be
blocks
contained in a boot block. The AT29C020 blocks are located in the first 8K bytes of memory and the last 8K bytes
of memory. The boot block programming lockout feature
can therefore support systems that boot from the lower
addresses of memory or the higher addresses. Once the
programming lockout feature has been activated, the data
in that block can no longer be erased or programmed;
data in other memory locations can st ill be changed
through the regular programming methods. To activate the
lockout feature, a series of seven program commands to
specific addresses with specific data must be performed.
Please see Boot Block Lockout Feature Enable Algorithm.
If the boot block lockout featu re has been activated on
either block, the chip erase function will be disabled.
BOOT BLOCK LOCKOUT DETECTION:
method is available to determine whether programming of
In addition to
DATA polling the
The entire device
DATA polling
The
boot
A software
(continued)
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or an y ot he r con ditions beyond t ho se ind icated in the oper ational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
3
µ
µ
µ
µ
Device Operation
(Continued)
either boot block section is locked out. See Software Product Identification Entry and Exit sections. When the device
is in the software product identification mode, a read from
location 00002H will show if programming the lower address boot block is locked out wh ile reading location
FFFF2H will do so for the upper boot block. If the data is
DC and AC Operating Range
AT29C020-90 AT29C020-10 AT29C020-12 AT29C020-15
Operating
Temperature (Case)
V
Power Supply 5V
CC
Com. 0°C - 70°C0
Ind. -40°C - 85°C-40
10% 5V
±
Operating Modes
FE, the corresponding block can be programmed; if the
data is FF, the program lockout feature has been activated
and the corresponding block cannot be programmed. The
software product identification exit mode should be used
to return to standard operation.
C - 70°C0
°
10% 5V ± 10% 5V ± 10%
±
C - 70°C0
°
C - 85°C-40
°
C - 70°C
°
C - 85°C
°
Mode
Read V
Program
(2)
5V Chip Erase V
Standby/Write Inhibit V
CE OE WE
IL
V
IL
IL
IH
V
V
V
X
IL
IH
IH
(1)
Program Inhibit X X V
Program Inhibit X V
Output Disable X V
IL
IH
V
IH
V
IL
V
IL
X X High Z
IH
X
X High Z
Ai I/O
Ai D
Ai D
OUT
IN
Ai
Product Identification
(3)
Manufacturer Code
Device Code
Manufacturer Code
Device Code
(4)
(4)
Hardware V
Software
Notes: 1. X can be VIL or VIH.
(5)
2. Refer to AC Programming Waveforms.
= 12.0V ± 0.5V.
3. V
H
A1 - A17 = VIL, A9 = VH,
IL
V
IL
V
IH
A1 - A17 = VIL, A9 = VH,
4. Manufacturer Code: 1F, Device Code: DA
5. See details unde r Soft ware Produ ct Ide nt if icat io n Ent ry/ Exit.
A0 = V
A0 = V
A0 = V
A0 = V
IL
IH
IL
IH
DC Characteristics
Symbol Parameter Condition Min Max Units
I
LI
I
LO
I
SB1
I
SB2
I
CC
V
IL
V
IH
V
OL
V
OH1
V
OH2
Input Load Current VIN = 0V to V
Output Leakage Current V
VCC Standby Current CMOS CE = V
VCC Standby Current TTL CE = 2.0V to V
V
Active Current f = 5 MHz; I
CC
Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA .45 V
Output High Voltage IOH = -400 µA2.4V
Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V
= 0V to V
I/O
CC
CC
CC
- 0.3V to V
OUT
CC
CC
= 0 mA 40 mA
Com. 100
Ind. 300
10
10
3mA
(4)
(4)
A
A
A
A
4
AT29C020
AC Read Characteristics
Symbol Parameter
t
ACC
(1)
t
CE
(2)
t
OE
(3, 4)
t
DF
t
OH
Address to Output Delay 0 90 100 120 150 ns
CE to Output Delay 90 100 120 150 ns
OE to Output Delay 040050050070 ns
CE or OE to Output Float 025025030040 ns
Output Hold from OE, CE or
Address, whichever
occurred first
AT29C020
AT29C020-90 AT29C020-10 AT29C020-12 AT29C020-15
MinMaxMinMaxMinMaxMinMax
0000 ns
Units
AC Read Waveforms
Notes: 1. CE may be delayed up to t
transition without impact on t
OE may be delayed up to tCE - tOE after the falling
2.
edge of
after an address change without impact on t
CE without impact on tCE or by t
(1, 2, 3, 4)
- tCE after the address
ACC
.
ACC
ACC
- tOE
ACC
3. t
DF
(C
L
4. This parameter is characterized and is not 100% tested.
.
Input Test Waveforms and Measurement Level
is specified from OE or CE whichever occurs first
= 5 pF).
Output Test Load
tR, tF < 5 ns
Note: While CE is active, any address inputs that cause VIH to drop
below 2.0V or V
may cause the devi ce t o read incorrectl y.
Pin Capacitance
to rise above 0.8V for a duration of up to 15 ns
IL
(f = 1 MHz, T = 25°C)
(1)
Typ Max Units Conditions
C
IN
C
OUT
Note: 1. This parameter is characterized and is not 100% tested.
46pFV
812pFV
= 0V
IN
= 0V
OUT
5
AC Byte Load Characteristics
Symbol Parameter Min Max Units
t
AS
t
AH
t
CS
t
CH
t
WP
t
DS
t
DH
t
WPH
, t
, t
OES
OEH
Address, OE Set-up Time 0 ns
Address Hold Time 50 ns
Chip Select Set-up Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE) 90 ns
Data Set-up Time 50 ns
Data, OE Hold Time 0 ns
Write Pulse Width High 100 ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
6
AT29C020
µ
AT29C020
Program Cycle Characteristics
Symbol Parameter Min Max Units
t
WC
t
AS
t
AH
t
DS
t
DH
t
WP
t
BLC
t
WPH
Write Cycle Time 10 ms
Address Set-up Time 0 ns
Address Hold Time 50 ns
Data Set-up Time 50 ns
Data Hold Time 0 ns
Write Pulse Width 90 ns
Byte Load Cycle Time 150
Write Pulse Width High 100 ns
Program Cycle Waveforms
s
(1, 2, 3)
Notes: 1. A8 through A17 must specify the sector address
during each high to low transition of WE (or CE).
2.
OE must be high when WE and CE are both low.
3.
All bytes that are not loaded within the sector being
programmed will be indeterminate.
7
Software Data
Protection Enable
Algorithm
(1)
Software Data
Protection Disable
Algorithm
(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA
TO
SECTOR (256 BYTES)
WRITES ENABLED
ENTER DATA
(4)
PROTECT STATE
(2)
Notes for software program code:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Data Protect state will be act iv at ed at en d of program cycle.
3. Data Protect state will be deactivated at end of program
period.
4. 256-bytes of data
MUST BE
loaded.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA
TO
SECTOR (256 BYTES)
EXIT DATA
PROTECT STATE
(4)
(3)
Software Protected Program Cycle Waveform
3.
Notes: 1. A8 through A17 must specify the sector address
during each high to low transition of
WE (or CE)
after the software cod e ha s be en ent ere d.
2. OE must be high when WE and CE are both low.
All bytes that are not loaded within the sector being
programmed will be indeterminate.
(1, 2, 3)
8
AT29C020
AT29C020
Data Polling Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
WR
Notes: 1. These parameters are characterized and no t 10 0% tes te d.
2. See t
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
Write Recovery Time 0 ns
spec in AC Read Charact eri stics.
OE
Data Polling Waveforms
ns
Toggle Bit Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
OEHP
t
WR
Notes: 1. These parameters are characterized and no t 10 0% tes te d.
2. See t
Toggle Bit Waveforms
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
OE High Pulse 150 ns
Write Recovery Time 0 ns
spec in AC Read Charact eri stics.
OE
(1, 2, 3)
ns
Notes: 1. Toggling either OE or CE or both OE and CE will
operate toggle bit.
2. Beginning and endi ng state of I/O6 will va ry.
3. Any address location may be use d but the address
should not vary.
9
Software Product
Identification Entry
(1)
Boot Block Lockout
Feature Enable Algorithm
(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
PAUSE 10 mS
Software Product
Identification Exit
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 10 mS
(1)
ENTER PRODUCT
IDENTIFICATION
(2, 3, 5)
MODE
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA 00
TO
ADDRESS 00000H
PAUSE 10 mS
(2)
LOAD DATA FF
TO
ADDRESS FFFFFH
PAUSE 10 mS
Notes for boot block lockout feature enable:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Lockout featur e set on lower address boot block.
3. Lockout featur e set on higher address boot block.
(3)
Notes for software product identification:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A17 = V
Manufacture Code is read for A0 = V
Device Code is read for A0 = V
.
IL
;
IL
.
IH
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1F
Device Code: DA
10
AT29C020
Ordering Information
AT29C020
t
ACC
(ns)
90 40 0.1 AT29C020-90JC 32J Commercial
100 40 0.1 AT29C020-10JC 32J Commercial
120 40 0.1 AT29C020-12JC 32J Commercial
150 40 0.1 AT29C020-15JC 32J Commercial
I
(mA)
CC
Active Standby
40 0.3 AT29C020-10JI 32J Industrial
40 0.3 AT29C020-12JI 32J Industrial
40 0.3 AT29C020-15JI 32J Industrial
Ordering Code Package Operation Range
AT29C020-90PC 32P6 (0° to 70°C)
AT29C020-90TC 32T
AT29C020-10PC 32P6 (0° to 70°C)
AT29C020-10TC 32T
AT29C020-10PI 32P6 (-40° to 85°C)
AT29C020-10TI 32T
AT29C020-12PC 32P6 (0° to 70°C)
AT29C020-12TC 32T
AT29C020-12PI 32P6 (-40° to 85°C)
AT29C020-12TI 32T
AT29C020-15PC 32P6 (0° to 70°C)
AT29C020-15TC 32T
AT29C020-15PI 32P6 (-40° to 85°C)
AT29C020-15TI 32T
32J
32P6
32T
Package Type
32 Lead, Plastic J-Leaded Chip Carrier (PLCC)
32 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32 Lead, Thin Small Outline Package (TSOP)
11
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