ATMEL AT29C010A-12PC, AT29C010A-12JI, AT29C010A-12JC, AT29C010A-90TI, AT29C010A-90TC Datasheet

1 Megabit
(128K x 8)
5-volt Only
CMOS Flash
Memory

Features

0394B

Fast Read Access Time - 70 ns

•

5-Volt-Only Reprogramming

•

Sector Program Operatio n

•

Single Cycle Repro gra m (Eras e and Program)
1024 Sectors (128 bytes /s ec tor)
Internal Address and Data Latches for 128-Bytes

Two 8 KB Boot Blocks with Lockout

•

Internal Program Control and Timer

•

Hardware and Software Data Protection

•

Fast Sector Program Cycl e Ti me - 10 ms

•

DATA Polling for End of Program Detec tio n

•

Low Power Dissipation

•

50 mA Active Current
100 µA CMOS Standby Current

Typical Endurance > 10,000 Cycles

•

Single 5V ±10% Sup pl y

•

CMOS and TTL Compatible Inputs and Outputs

•

Commercial and Industrial Temperature Ranges

•

Description

The AT29C010A is a 5-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 1 megabit of memory is organized as 131,072 words by 8
bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 70 ns with power dissipation of just 275 mW over the commer­cial temperature range. When the device is deselected, the CMOS standby curr ent is
less than 100 µA. The device endurance is such that any sector can typically be writ­ten to in excess of 10,000 times.

To allow for simple in-system reprogrammability, the AT29C010A does not require
high input voltages for programming. Five-volt-only commands determine the opera-

Pin Configurations

Pin Name Function

A0 - A16 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
I/O0 - I/O7 Data Inputs/Output s
NC No Connect

DIP Top View

(continued)

AT29C010A

AT29C010A

PLCC Top View

TSOP Top View

Type 1

4-129

Description (Continued)

tion of the device. Reading data out of the device is similar
to reading from an EPROM. Reprogramming the
AT29C010A is performed on a sector basis; 128-bytes of
data are loaded into the device and then simultaneously
programmed.

During a reprogram cycle, the address locations and 128­bytes of data are internally latched, freeing the address

Block Diagram

Device Operation

READ: The A T29C010A is accessed like an EPROM.

CE and OE are low and WE is high, the data stored

When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever
line control gives designers flexibility in preventing bus
contention.

BYTE LOAD: Byte loads are used to enter the 128­bytes of a sector to be programmed or the software codes
for data protection. A byte load is performed by applying a
low pulse on the
spectively) and
falling edge of
is latched by the first rising edge of

PROGRAM: The device is reprogrammed on a sector
basis. If a byte of data within a sector is to be changed,
data for the entire sector must be loaded into the device.
The data in any byte that is not loaded during the program­ming of its sector will be indeterminate. Once the bytes of
a sector are loaded into the device, they are simultane­ously program med during the internal programming pe­riod. After the first data byte has been loaded into the de­vice, successive bytes are entered in the same manner.
Each new byte to be programmed must have its high to
low transition on
high transition of
high to low transition is not detected within 150 µs of the
last low to high transition, the load period will end and the
internal programming period will start. A7 to A16 specify
the sector address. The sector address must be valid dur­ing each high to low transition of
specify the byte address within the sector. The bytes may

WE or CE input with CE or WE low (re-

OE high. The address is latched on the

CE or WE, whichever occurs last. The data

WE (or CE) within 150 µs of the low to

WE (or CE) of the preceding byte. If a

CE or OE is high. This dual-

CE or WE.

WE (or CE). A0 to A6

and data bus for other operations. Following the initiation
of a program cycle, the device will automatically erase the
sector and then program the latched data using an internal
control timer. The end of a program cycle can be detected

DATA polling of I/O7. Once the end of a program cycle

by
has been detected, a new access for a read or program
can begin.

be loaded in any order; sequential loading is not required.
Once a programming operation has been initiated, and for
the duration of t
polling operation.

SOFTWARE DATA PROTECTION: A software control­led data protection feature is available on the AT29C010A.
Once the software protection is enabled a software algo­rithm must be issued to the device before a program may
be performed. The software protection feature may be en­abled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable
the software data protection, a series of three program
commands to specific addresses with specific data must
be performed. After the software data protection is en­abled the sa me three program com mands must begin
each program cycle in order for the programs to occur. Al l
software program commands must obey the sector pro­gram timing specifications. Once set, the software data
protection feature remains active unless its disable com­mand is issued. Power transitions will not reset the soft­ware data protection feature, however the software fea­ture will guard against inadvertent program cycles during
power transitions.

Once set, software data protection will remain active un­less the disable command sequence is issued.

After setting SDP, any attempt to write to the device with­out the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of t
a polling operation.

, a read operation will effectively be a

WC

, a read operation will effectively be

WC

(continued)

4-130 AT29C010A

Device Operation (Continued)

After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the
and
CE or WE, whichever occurs last. The data is latched by
the first rising edge of
must be loaded into each sector by the same procedure as
outlined in the program section under device operation.

HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29C010A
in the following ways: (a) V
(typical), the program function is inhibited. (b) V
on delay— once V
the device will automatically time out 5 ms (typical) before
programming. (c) Program inhibit— holding any one of
low,
filter— pulses of less than 15 ns (typical) on the
inputs will not initiate a program cycle.

PRODUCT IDE NTIFICATION: The product identifica­tion mode identifies the device and manufacturer as At­mel. It may be accessed by hardware or software opera­tion. The hardware operation mode can be us ed by an ex­ternal programmer to identify the correct programming al­gorithm for the Atmel product. In addition, users may wish
to use the software product identification mode to identify
the part (i.e. using the device code), and have the system
software use the appropriate sector size for program op­erations. In th is manner, the user can have a common
board design for 256K to 4-megabit densities and, with
each density’s sector size in a memory map, have the sys­tem software apply the appropriate sector size.

For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING: The AT29C010A features DATA poll­ing to indicate the end of a program cycle. During a pro­gram cycle an attempted read of the last byte loaded will

WE or CE input with CE or WE low (respectively)

OE high. The address is latched on the falling edge of

CE or WE. The 128-bytes of data

sense— if VCC is below 3.8V

CC

power

CC

has reached the VCC sense level,

CC

OE

CE high or WE high inhibits program cycles. (d) Noise

WE or CE

Absolute Maximum Ratings*

Temperature Under Bias.................-55°C to +125°C

AT29C010A

result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin.
may begin at any time during the program cycle.

TOGGLE BIT: In addition to
AT29C010A provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.

OPTIONAL CHIP ERASE MODE: The entire device
can be erased by using a 6-byte software code. Please
see Software Chip Erase application note for details.

BOOT BLOCK PROGRAMMING LOCKOUT: The
AT29C010A has two designated memory blocks that have
a programming lockout feature. This feature prevents pro­gramming of data in the designated block once the feature
has been enabled. Each of these blocks consists of 8K
bytes; the programming lockout feature can be set inde­pendently for either block. While the lockout feature does
not have to be activated, it can be activated for either or
both blocks.

These two 8K memory sections are referred to as

. Secure code which will bring up a system can be

blocks

contained in a boot block. The AT29C010A blocks are lo­cated in the first 8K bytes of memory and the last 8K bytes
of memory. The boot block programming lockout feature
can therefore support systems that boot from the lower
addresses of memory or the higher addresses. Once the
programming lockout feature has been activated, the data
in that block can no longer be erased or programmed;
data in other memory locations can st ill be changed
through the regular programming methods. To activate the
lockout feature, a series of seven program commands to
specific addresses with specific data must be performed.
Please see Boot Block Lockout Feature Enable Algorithm.

If the boot block lockout feature has been activated on
either block, the chip erase function will be disabled.

DATA p o l li n g th e

DATA polling

boot

Storage Temperature...................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground .............-0.6V to V

Voltage on OE

with Respect to Ground ................... -0.6V to +13.5V

+ 0.6V

CC

(continued)

*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-

mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi­cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

4-131

Device Operation (Continued)

BOOT BLOCK LOCKOUT DETECTION: A software

method is available to determine whether programming of
either boot block section is locked out. See Software Prod­uct Identification Entry and Exit sections. When the device
is in the software product identification mode, a read from
location 00002 will show if programming the lower address
boot block is locked out while reading location FFFF2 will

do so for the upper boot block. If the data is FE, the corre­sponding block can be programmed; if the data is FF, the
program lockout feature has been activated and the corre­sponding block cannot be programmed. The software
product identification exit mode should be used to return to
standard operation.

DC and AC Operating Range

AT29C010A-70 AT29C010A-90 AT29C010A-12 AT29C010A-15

Operating
Temperature (Case)

V

Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10%

CC

Com. 0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C
Ind. -40°C - 85°C-40°C - 85°C-40°C - 85°C

Operating Modes

Mode CE OE WE Ai I/O

Read V
Program

(2)

5V Chip Erase V
Standby/Write Inhibit V

IL

V

IL
IL

IH

Program Inhibit X X V
Program Inhibit X V
Output Disable X V

V
V
V

X

IL
IH
IH

(1)

IL
IH

V

IH

V

IL

V

IL

X X High Z

IH

X
X High Z

Ai D
Ai D
Ai

OUT
IN

Product Identification

(3)

Manufacturer Code

(3)

Device Code
Manufacturer Code

Device Code

Hardware V

Software

Notes: 1. X can be VIL or VIH.

(5)

2. Refer to AC Programming Waveforms.

3. V

= 12.0V ± 0.5V.

H

A1 - A16 = VIL, A9 = VH,

IL

V

IL

V

IH

A1 - A16 = VIL, A9 = VH,

4. Manufacturer Code: 1F, Device Code: D5

5. See details unde r Soft ware Product Identific at io n Ent ry/ Exit.

A0 = V
A0 = V

A0 = V
A0 = V

IL

IH
IL

IH

DC Characteristics

(4)

(4)

(4)

(4)

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

CC

V

IL

V

IH

V

OL

V

OH1

V

OH2

Input Load Current VIN = 0V to V
Output Leakage Current V

VCC Standby Current CMOS CE = V

= 0V to V

I/O

CC

- 0.3V to V

VCC Standby Current TTL CE = 2.0V to V
V

Active Current f = 5 MHz; I

CC

OUT

CC

CC

CC

CC

Com. 100 µA
Ind. 300 µA

= 0 mA 50 mA

10 µA
10 µA

3mA

Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA .45 V
Output High Voltage IOH = -400 µA 2.4 V
Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

4-132 AT29C010A