ATMEL AT29BV040A User Manual

BDTIC www.BDTIC.com/ATMEL

Features

Single Supply Voltage, Range 2.7V to 3.6V
Single Supply for Read and Write
Software Protected Programming
Fast Read Access Time – 200 ns
Low Power Dissipation
– 15 mA Active Current – 50 µA CMOS Standby Current
– Single Cycle Reprogram (Erase and Program) – 2048 Sectors (256 Bytes/Sector) – Internal Address and Data Latches for 256 Bytes
Two 16K Bytes Boot Blocks with Lockout
Fast Sector Program Cycle Time – 20 ms Max.
Internal Program Control and Timer
DATA Polling for End of Program Detection
Minimum Endurance 10,000 Cycles
CMOS and TTL Compatible Inputs and Outputs
Green (Pb/Halide-free) Packaging Option
4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory

1. Description

The AT29BV040A is a 3-volt-only in-system Flash Programmable and Erasable Read Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology, the device offers access times to 200 ns, and a low 54 mW power dissipation. When the device is deselected, the CMOS standby current is less than 50 µA. The device endurance is such that any sector can be written to in excess of 10,000 times. The programming algorithm is compatible with other devices in Atmel’s 2.7-volt-only Flash memories.
To allow for simple in-system reprogrammability, the AT29BV040A does not require high input voltages for programming. The device can be operated with a single 2.7V to
3.6V supply. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29BV040A is performed on a sector basis; 256 bytes of data are loaded into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 256 bytes of data are captured at microprocessor speed and internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automati­cally erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA end of a program cycle has been detected, a new access for a read or program can begin.
polling of I/O7. Once the
AT29BV040A
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2. Pin Configurations

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A11
A9
A8 A13 A14 A17
WE
VCC
A18 A16 A15 A12
A7
A6
A5
A4
OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
5 6 7 8 9 10 11 12 13
29 28 27 26 25 24 23 22 21
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A14 A13 A8 A9 A11 OE A10 CE I/O7
4
3
2
1
323130
14151617181920
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A12
A15
A16
A18
VCCWEA17
Pin Name Function
A0 - A18 Addresses
CE
Chip Enable
OE
WE
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect

2.1 32-lead TSOP (Type 1) Top View

Output Enable
Write Enable

2.2 32-lead PLCC Top View

2
AT29BV040A
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3. Block Diagram

4. Device Operation

4.1 Read

The AT29BV040A is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE trol gives designers flexibility in preventing bus contention.
AT29BV040A
or OE is high. This dual-line con-

4.2 Software Data Protection Programming

The AT29BV040 has 2048 individual sectors, each 256 bytes. Using the software data protec­tion feature, byte loads are used to enter the 256 bytes of a sector to be programmed. The AT29BV040A can only be programmed or reprogrammed using the software data protection feature. The device is programmed on a sector basis. If a byte of data within the sector is to be changed, data for the entire 256-byte sector must be loaded into the device. The AT29BV040A automatically does a sector erase prior to loading the data into the sector. An erase command is not required.
Software data protection protects the device from inadvertent programming. A series of three program commands to specific addresses with specific data must be presented to the device before programming may occur. The same three program commands must begin each program operation. All software program commands must obey the sector program timing specifications. Power transitions will not reset the software data protection feature, however the software fea­ture will guard against inadvertent program cycles during power transitions.
Any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of t tion will effectively be a polling operation.
After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE address is latched on the falling edge of CE the first rising edge of CE
or WE.
, a read opera-
WC
or CE input with CE or WE low (respectively) and OE high. The
or WE, whichever occurs last. The data is latched by
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The 256 bytes of data must be loaded into each sector. Any byte that is not loaded during the programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the
3
first data byte has been loaded into the device, successive bytes are entered in the same man­ner. Each new byte to be programmed must have its high-to-low transition on WE 150 µs of the low-to-high transition of WE tion is not detected within 150 µs of the last low-to-high transition, the load period will end and the internal programming period will start. A8 to A18 specify the sector address. The sector address must be valid during each high-to-low transition of WE byte address within the sector. The bytes may be loaded in any order; sequential loading is not required.

4.3 Hardware Data Protection

Hardware features protect against inadvertent programs to the AT29BV040A in the following ways: (a) V power on delay – once VCC has reached the VCC sense level, the device will automatically time out 10 ms (typical) before programming; (c) Program inhibit – holding any one of OE high or WE high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the WE
CC
or CE inputs will not initiate a program cycle.

4.4 Input Levels

While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to V
(or CE) within
(or CE) of the preceding byte. If a high-to-low transi-
(or CE). A0 to A7 specify the
sense – if VCC is below 1.8V (typical), the program function is inhibited; (b) V
low, CE
+ 0.6V.
CC
CC

4.5 Product Identification

The product identification mode identifies the device and manufacturer as Atmel®. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish to use the software product identification mode to identify the part (i.e. using the device code), and have the system software use the appropriate sector size for program operations. In this manner, the user can have a common board design for 256K to 4-megabit densities and, with each density’s sector size in a memory map, have the system soft­ware apply the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.

4.6 DATA Polling

The AT29BV040A features DATA polling to indicate the end of a program cycle. During a pro­gram cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA

4.7 Toggle Bit

In addition to DATA polling the AT29BV040A provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
polling may begin at any time during the program cycle.
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4.8 Optional Chip Erase Modes

The entire device may be erased by using a 6-byte software code. Please see Software Chip Erase application note for details.

4.9 Boot Block Programming Lockout

The AT29BV040A has two designated memory blocks that have a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. Each of these blocks consists of 16K bytes; the programming lockout feature can be set independently for either block. While the lockout feature does not have to be activated, it can be activated for either or both blocks.
These two 16K memory sections are referred to as boot blocks. Secure code which will bring up a system can be contained in a boot block. The AT29BV040A blocks are located in the first 16K bytes of memory and the last 16K bytes of memory. The boot block programming lockout feature can therefore support systems that boot from the lower addresses of memory or the higher addresses. Once the programming lockout feature has been activated, the data in that block can no longer be erased or programmed; data in other memory locations can still be changed through the regular programming methods. To activate the lockout feature, a series of seven program commands to specific addresses with specific data must be performed. Please see Boot Block Lockout Feature Enable Algorithm.
AT29BV040A
If the boot block lockout feature has been activated on either block, the chip erase function will be disabled.

4.9.1 Boot Block Lockout Detection

A software method is available to determine whether programming of either boot block section is locked out. See Software Product Identification Entry and Exit sections. When the device is in the software product identification mode, a read from location 00002H will show if programming the lower address boot block is locked out while reading location 7FFF2H will do so for the upper boot block. If the data is FE, the corresponding block can be programmed; if the data is FF, the program lockout feature has been activated and the corresponding block cannot be pro­grammed. The software product identification exit mode should be used to return to standard operation.

5. Absolute Maximum Ratings*

Temperature Under Bias............................... -55° C to +125°C
Storage Temperature .................................... -65°C to +150° C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Voltage on A9 (including NC Pins)
with Respect to Ground ...................................-0.6V to +13.5V
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6. DC and AC Operating Range

AT29BV040A-20
Operating Temperature (Case) Industrial -40°C - 85°C
VCC Power Supply
(1)
2.7V to 3.6V
Note: 1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an opera-
tional mode is started.

7. Operating Modes

Mode CE OE WE Ai I/O
X
V
IL
V
IH
(1)
Read V
Program
(2)
Standby/Write Inhibit V
IL
V
IL
IH
Program Inhibit X X V
Program Inhibit X V
Output Disable X V
IL
IH
Product Identification
Hardware V
Software
Notes: 1. X can be V
(5)
or VIH.
IL
IL
V
IL
2. Refer to AC Programming Waveforms.
3. V
= 12.0V ± 0.5V.
H
4. Manufacturer Code is 1F. The Device Code is C4.
5. See details under Software Product Identification Entry/Exit.
V
IH
V
IL
Ai D
Ai D
OUT
X X High Z
IH
X
X High Z
V
A1 - A18 = VIL, A9 = V
IH
A1 - A18 = VIL, A9 = V
A0 = V
A0 = V
A1 - A18 = V
IL,
A1 - A18 = V
IH,
(3)
H
(3)
H
, A0 = V
, A0 = V
IL
IL
Manufacturer Code
IL
IH
Device Code
Manufacturer Code
Device Code
IN
(4)
(4)
(4)
(4)

8. DC Characteristics

Symbol Parameter Condition Min Max Units
I
LI
I
LO
Input Load Current VIN = 0V to V
Output Leakage Current V
= 0V to V
I/O
CC
CC
Com. 40 µA
I
SB1
I
SB2
I
CC
V
IL
V
IH
V
OL
V
OH
6
VCC Standby Current CMOS CE = V
VCC Standby Current TTL CE = 2.0V to V
V
Active Current f = 5 MHz; I
CC
- 0.3V to V
CC
OUT
CC
CC
Ind. 50 µA
= 0 mA; VCC = 3.6V 15 mA
Input Low Voltage 0.6 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 1.6 mA; VCC = 3.0V 0.45 V
Output High Voltage IOH = -100 µA; VCC = 3.0V 2.4 V
AT29BV040A
A
A
1mA
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9. AC Read Characteristics

Symbol Parameter
AT29BV040A
AT29BV040A-20
UnitsMin Max
t
t
t
t
t
ACC
CE
OE
DF
OH
(1)
(2)
(3)(4)
Address to Output Delay 200 ns
CE to Output Delay 200 ns
OE to Output Delay 0 80 ns
CE or OE to Output Float 0 50 ns
Output Hold from OE, CE or Address, whichever occurred first

10. AC Read Waveforms

0ns
Notes: 1. CE may be delayed up to t
2. OE
may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by t
without impact on t
3. t
is specified from OE or CE whichever occurs first (CL = 5 pF).
DF
ACC
.
4. This parameter is characterized and is not 100% tested.
- tCE after the address transition without impact on t
ACC
ACC
.
- tOE after an address change
ACC
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7

11. Input Test Waveforms and Measurement Level

tR, tF < 5 ns

12. Output Test Load

13. Pin Capacitance

f = 1 MHz, T = 25°C
Symbol Typ Max Units Conditions
C
IN
C
OUT
Note: 1. These parameters are characterized and not 100% tested.
(1)
46pFV
812pFV
IN
OUT
= 0V
= 0V
8
AT29BV040A
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AT29BV040A

14. AC Byte Load Characteristics

Symbol Parameter Min Max Units
t
AS
t
AH
t
CS
t
CH
t
WP
t
DS
t
DH
t
WPH
, t
OES
, t
OEH
Address, OE Set-up Time 10 ns
Address Hold Time 100 ns
Chip Select Set-up Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE)200ns
Data Set-up Time 100 ns
Data, OE Hold Time 10 ns
Write Pulse Width High 200 ns
15. AC Byte Load Waveforms

15.1 WE Controlled

15.2 CE Controlled

(1)(2)
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9

16. Program Cycle Characteristics

LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA
TO
SECTOR (256 BYTES)
(3)
WRITES ENABLED
ENTER DATA PROTECT STATE
(2)
Symbol Parameter Min Max Units
t
WC
t
AS
t
AH
t
DS
t
DH
t
WP
t
BLC
t
WPH
Write Cycle Time 20 ms
Address Set-up Time 10 ns
Address Hold Time 100 ns
Data Set-up Time 100 ns
Data Hold Time 10 ns
Write Pulse Width 200 ns
Byte Load Cycle Time 150 µs
Write Pulse Width High 200 ns

17. Software Protected Program Waveform

Notes: 1. OE must be high when WE and CE are both low.
18. Programming Algorithm
Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex).
10
2. A8 through A18 must specify the sector address during each high to low transition of WE been entered.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.
(1)
2. Data Protect state will be re-activated at end of program cycle.
3. 256 bytes of data MUST BE loaded.
AT29BV040A
(or CE) after the software code has
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AT29BV040A
19. Data Polling Characteristics
(1)(2)
Symbol Parameter Min Typ Max Units
t
t
t
t
DH
OEH
OE
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See t
spec in AC Read Characteristics.
OE

20. Data Polling Waveforms

ns
21. Toggle Bit Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
OEHP
t
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
OE High Pulse 150 ns
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
22. Toggle Bit Waveforms
(1)(3)
ns
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
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11
23. Software Product Identification
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
PAUSE 20 mS ENTER PRODUCT
IDENTIFICATION MODE
(2)(3)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 20 mS EXIT PRODUCT
IDENTIFICATION MODE
(4)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA 00
TO
ADDRESS 00000H
(2)
PAUSE 20 mS
LOAD DATA FF
TO
ADDRESS 7FFFFH
(3)
PAUSE 20 mS
Entry
(1)
24. Software Product Identification
(1)
Exit
25. Boot Block Lockout Feature Enable Algorithm
(1)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A18 = V Manufacturer Code is read for A0 = V Device Code is read for A0 = VIH.
.
IL
3. The device does not remain in identification mode if powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is C4.
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Lockout feature set on lower address boot block.
3. Lockout feature set on higher address boot block.
;
IL
12
AT29BV040A
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26. Ordering Information

26.1 Green Package Option (Pb/Halide-free)

I
t
ACC
(ns)
200 15 0.05
CC
(mA)
Ordering Code Package Operation RangeActive Standby
AT29BV040A-20JU AT29BV040A-20TU
32J 32T
AT29BV040A
Industrial
(-40° to 85° C)
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32T 32-lead, Thin Small Outline Package (TSOP)
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Package Type
13

27. Packaging Information

DRAWING NO.
REV.
2325 Orchard Parkway San Jose, CA 95131
R
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
B
32J
10/04/01
1.14(0.045) X 45˚
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1
E2
B
e
E1 E
D1
D
D2
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 3.175 3.556
A1 1.524 2.413
A2 0.381
D 12.319 12.573
D1 11.354 11.506 Note 2
D2 9.906 10.922
E 14.859 15.113
E1 13.894 14.046 Note 2
E2 12.471 13.487
B 0.660 0.813
B1 0.330 0.533
e 1.270 TYP

27.1 32J – PLCC

14
AT29BV040A
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27.2 32T – TSOP

2325 Orchard Parkway San Jose, CA 95131
TITLE
DRAWING NO.
R
REV.
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
B
32T
10/18/01
PIN 1
D1
D
Pin 1 Identifier
b
e
E
A
A1
A2
0º ~ 8º
c
L
GAGE PLANE
SEATING PLANE
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A 1.20
A1 0.05 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 0.21
e 0.50 BASIC
AT29BV040A
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15
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