ATMEL AT28LV010-25TI, AT28LV010-25TC, AT28LV010-25PI, AT28LV010-25PC, AT28LV010-25JI Datasheet
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AT28LV010
1 Megabit
(128K x 8)
Low Voltage
Paged CMOS
E2PROM
0395A
AT28LV010
Features
Single 3.3V ± 10% Supply
•
Fast Read Access Time - 200 ns
•
Automatic Page Write Operation
•
Internal Address and Data Latches for 128-Bytes
Internal Control Timer
Fast Write Cycle Tim e
•
Page Write Cycle Time - 10 ms Maximum
1 to 128-Byte Page Write Ope rati on
Low Power Dissipation
•
15 mA Active Current
20 µA CMOS Standby Current
Hardware and Software Data Protection
•
DATA Polling for End of Write Dete cti on
•
High Reliabili ty C MOS Technology
•
Endurance: 100, 000K Cycles
Data Retention: 10 Years
JEDEC Approved Byte-Wid e Pin ou t
•
Commercial and Industrial Temperature Ranges
•
Description
The AT28LV010 is a high-performance 3-volt only Electrically Erasable and Programmable Read Only Memory. Its 1 megabit of memory is organized as 131,072 words
by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the
device offers access times to 200 ns with power dissipation of just 54 mW. When the
device is deselected, the CMOS standby current is less than 20 µA.
Pin Configurations
(continued)
Pin Name Function
A0 - A16 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
I/O0 - I/O7
NC No Connect
DC Don’t Connec t
Top View
Data
Inputs/Outputs
PLCC
PDIP
Top View
TSOP
Top View
2-155
Description (Continued)
The AT28LV010 is accessed like a Static RAM for the
read or write cycle without the need for external components. The device contains a 128-byte page register to a llow writing of up to 128-bytes simultaneously. During a
write cycle, the address and 1 to 128-bytes of data are
internally latched, freeing the address and data bus for
other operations. Following the initiation of a write cycle,
the device will automatically write the latched data using
an internal control timer. The end of a write cycle can be
detected by
cycle has been detected a new access for a read or write
can begin.
DATA polling of I/O7. Once the end of a write
Block Diagram
Atmel’s 28LV010 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correc tion for extended endurance and improved
data retention characteristics. Software data protection is
implemented to guard against inadvertent writes. The device also includes an extra 128-bytes of E
vice identification or tracking.
2
PROM for de-
Absolute Maximum Ratings*
Temperature Under Bias.................-55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
Voltage on
with Respect to Ground ................... -0.6V to +13.5V
2-156 AT28LV010
OE and A9
+ 0.6V
CC
*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-
mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Device Operation
READ: The AT28LV010 is accessed like a Static RAM.
CE and OE are low and WE is high, the data stored
When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either
line control gives designers flexibility in preventing bus
contention in their system.
WRITE: The write operation of the AT28LV010 allows 1 to
128-bytes of data to be written into the device during a
single internal programming period. Each write operation
must be preceded by the software data protection (SDP)
command sequence. This sequence is a series of three
unique write command operations that enable the internal
write circuitry. The command sequence and the data to be
written must conform to the software protected write cycle
timing. Addresses are latched on the falling edge of
CE, whichever occurs last and data is latched on the rising
edge of
sive byte must be written within 150 µs (t
vious byte. If the t
cease accepting data and commence the interal programming operation. If more than one data byte is to be written
during a single programming operation, they must reside
on the same page as defined by the state of the A7 - A16
inputs. For each
write operation, A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
DATA POLLING: The AT28LV010 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complem ent of the written data to be presented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin.
write cycle.
WE or CE, whichever occurs first. Each succes-
limit is exceeded the AT28LV010 will
BLC
WE high to low transition during the page
DATA Polling may begin at anytime during the
CE or OE is high. This dual-
WE or
) of the pre-
BLC
AT28LV010
TOGGLE BIT: In addition to
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware
and software features that will protect the memory agains t
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28LV010 in the following ways: (a) V
2.0V (typical) the device will automatically time out 5 ms
(typical) before allowing a write: (b) write inhibit - holding
any one of
cles; (c) noise filter - pulses of less than 15 ns (typical) on
WE or CE inputs will not initiate a write cycle.
the
SOFTWARE DATA PROTECTION: The AT28LV010 in-
corporates the industry standard software data protection
(SDP) f unction. Unlike standard 5-volt o nly E
the AT28LV010 has SDP enabled at all times. Therefore,
all write operations must be preceded by the SDP command sequence.
The data in the 3-byte command sequence is not written
to the device; the addresses in the command sequence
can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte sequence will start the internal timers. No data will be written
to the device. However, for the duration of t
erations will effectively be polling operations.
power-on delay - once VCC has reached
CC
OE low, CE high or WE high inhibits write cy-
DATA Polling the AT28LV010
2
PROM’s,
, read op-
WC
2-157
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