ATMEL AT28HC256F-12LM-883, AT28HC256E-12LM-883, AT28HC256F-90LM-883, AT28HC256E-90LM-883, AT28HC256E-12SI Datasheet
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1
Features
•
Fast Read Access Time - 70 ns
•
Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
•
Fast Write Cycle Times
– Page Write Cycle Time: 3 ms or 10 ms Maximum
– 1 to 64-Byte Page Write Opera tion
•
Low Power Dissipation
– 80 mA Active Current
– 3 mA Standby Current
•
Hardware and Software Data Protection
•
DAT A Polling for End of Write Detection
•
High Reliability CMOS Technology
– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years
•
Single 5V ± 10% Supply
•
CMOS and TTL Compatible Inputs and Outputs
•
JEDEC Approved Byte-Wide Pinout
•
Full Military, Commercial, and Industrial Temperature Ranges
Description
The AT28HC256 is a high-performance Electrically Erasable and Programmable
Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256
256 (32K x 8)
High Speed
Parallel
EEPROMs
AT28HC256
Rev. 0007G–10/98
Pin Configurations
Pin Name Function
A0 - A14 Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect
TSOP
Top Vi ew
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
LCC, PLCC
Top View
Note: PLCC package pins 1 and
17 are DON’T CONNECT.
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
432
1
323130
14151617181920
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
A7
A12
A14DCVCCWEA13
PGA
Top View
(continued)
CERDIP, PDIP, FLATPACK
Top Vi ew
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
AT28HC256
2
offers access times to 70 ns with power dissipation of just
440 mW. When the AT28HC256 is deselected, the standby
current is less than 5 mA.
The AT28HC256 is accessed like a Static RAM for the read
or write cycle without the need for external components.
The device contains a 64-byte page register to allow writing
of up to 64 bytes simultaneously. During a write cycle, the
address and 1 to 64 bytes of data are inte rnally latched,
freeing the addresses and data bus for other operations.
Following the initiation of a write cycle, the device will automatically write the latched data using a n internal control
timer. The end of a write cycle can be detected by DATA
polling of I/O7. Once the end of a write c ycle has been
detected a new access for a read or write can begin.
Atmel’s 28HC256 has additional features to ensure hi gh
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved data
retention characteristics. An optional software data protection mechanism is available to guard against inadvertent
writes. The device also includes an extra 64 bytes of
EEPROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature Under Bias................................-55°C to +125°C
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the de vic e. T his is a stress r ating o nly an d
functional opera tion of the device at these or an y
other conditions beyond those indicated in the
operational sections of this specif ication is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reli abi li ty
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to V
CC
+ 0.6V
Voltage on OE
and A9
with Respect to Ground...................................-0.6V to +13.5V
AT28HC256
3
Device Operation
READ:
The AT28HC256 is accessed like a Static RAM.
When CE
and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE
or OE is high. This dualline control gives designers flexibility in preventing bus contention in their system.
BYTE WRITE:
A low pulse on the W E
or CE input with CE
or WE low (respec tive ly) and OE high initiates a write cycle.
The address is latched on the fallin g edge of CE
or WE,
whichever occurs last. The data is latched by the first rising
edge of CE
or WE. Once a byte write has been started it
will automatically time itself to completion. Once a programming operation has be en in itiated and for the du ratio n
of t
WC
, a read operation will effectively be a polling opera-
tion.
PAGE WRITE:
The page write operation of the
AT28HC256 allows 1 to 64 bytes of data to be written into
the device during a single internal pr ogramming period. A
page write oper ation is in itiated in the same mann er as a
byte write; the first byte written can then be followed by 1 to
63 additional bytes. Each successive byte must be written
within 150 µs (t
BLC
) of the previous byte. If the t
BLC
limit is
exceeded the AT28C256 will cease accepting data and
commence the internal programming operation. All bytes
during a page write operation must reside on the same
page as defined by the state of the A6 - A14 inputs. That is,
for each WE
high to low transition during the p age write
operation, A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes wi thin
the page are to be written. The bytes may be loade d in any
order and may be altered within the same load period. Only
bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not
occur.
DATA
POLLING:
The AT28HC256 features DATA
Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O
7
. Once the write cycle has been completed, true
data is valid on all outputs, and the next write cycle may
begin. DATA
Polling may beg in at an ytim e du ring the wr ite
cycle.
TOGGLE BIT:
In addition to DATA
Polling the AT28HC256
provides another m etho d for d ete rm ining the end of a wr it e
cycle. During the write operation, successive attempts to
read data from the device will result in I/O
6
toggling
between one and z ero. O nc e the wri te has c om pl eted , I /O
6
will stop toggling and valid data will be read. Testing the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION:
If precautions are not taken, inad-
vertent writes to any 5-volt-only nonvolatile memory may
occur during transition of the host system power supply.
Atmel has incorporated both hardware and software features that will protect the mem ory against inadvertent
writes.
HARDWARE PROTECTION:
Hardware features protect
against inadvert ent writ es to the AT 28HC25 6 in the fol lowing ways: (a) V
CC
sense—if VCC is below 3.8V (typi cal) th e
write function is inhibited; (b) V
CC
power-on delay—once
V
CC
has reached 3.8V the device will automatically time out
5 ms typical) before allowing a writ e; (c) wri te in hi bit —hol ding any one of OE
low, CE high or WE high inhib its write
cycles; and (d) noise filter— pulses of les s than 15 ns (typ ical) on the WE
or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION:
A software controlled
data protection feat ure has been implemente d on the
AT28HC256. When enabled, the s oftware data p rotection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28HC256 is
shipped from Atmel with SDP disabled.
SDP is enabled by the host system issuing a series of three
write commands; thre e specifi c bytes of dat a are written to
three specific addre sses (re fer to Soft ware Da ta Pro tection
Algorithm). After writing the 3-byte command sequence
and after t
WC
the entire AT 28HC256 will be protected
against inadverte nt write oper ations. It sho uld be note d,
that once protected the host may still perform a byte or
page write to the AT 28HC256. T his is done by pr eceding
the data to be written by the same 3-byte command
sequence.
Once set, SDP will remain activ e unless the disable c ommand sequence is i ssue d. P owe r trans iti ons do not disable
SDP and SDP will protect the AT28HC256 during power-up
and power-down conditions . A ll com man d s eque nc es mus t
conform to the page write timing specifications. It should
also be noted that the data in the enabl e and disa ble command sequences is not wr itten to th e devi ce and the memory addresses used in the sequence may be written with
data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without
the three byte command sequence will star t the i nternal
write timers. No data will be writte n to t he d evi c e; ho wever,
for the duration of t
WC
, read operations will effectively be
polling operations.
DEVICE IDENTIFICATION:
An extra 64 bytes of EEPROM
memory are available to the user for devi ce identificatio n.
By raising A9 to 12V ± 0.5V and using address locations
7FC0H to 7FFFH the add itional byt es may be writt en to or
read from in the same manner as the regular memory
array.
OPTIONAL CHIP ERASE MODE:
The entire device can
be erased using a 6-byte software code. Please see Software Chip Erase application note for details.
AT28HC256
4
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. V
H
= 12.0V ± 0.5V.
DC and AC Operating Range
AT28HC256-70 AT28HC256-90 AT28HC256-12
Operating
Temperature (Case)
Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C
Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C
Mil. -55°C - 125°C -55°C - 125°C
V
CC
Power Supply 5V ± 10% 5V ± 10% 5V ± 10%
Operating Modes
Mode CE OE WE I/O
Read V
IL
V
IL
V
IH
D
OUT
Write
(2)
V
IL
V
IH
V
IL
D
IN
Standby/Write Inhibit V
IH
X
(1)
XHigh Z
Write Inhibit X X V
IH
Write Inhibit X V
IL
X
Output Disable X V
IH
XHigh Z
Chip Erase V
IL
V
H
(3)
VIL High Z
DC Characteristics
Symbol Parameter Condition Min Max Units
I
LI
Input Load Current VIN = 0V to VCC + 1V 10 µA
I
LO
Output Leakage Current V
I/O
= 0V to V
CC
10 µA
I
SB1
VCC Standby Current TTL CE = 2.0V to VCC + 1V
AT28HC256-90, -12 3 mA
AT28HC256-70 60 mA
I
SB2
VCC Standby Current CMOS CE = -3.0V to VCC + 1V AT28HC256-90, -12 300 µA
I
CC
V
CC
Active Current f = 5 MHz; I
OUT
= 0 mA 80 mA
V
IL
Input Low Voltage 0.8 V
V
IH
Input High Voltage 2.0 V
V
OL
Output Low Voltage IOL = 6.0 mA 0.45 V
V
OH
Output High Voltage I
OH
= -4 mA 2.4 V
AT28HC256
5
AC Read Waveforms
(1)(2)(3)(4)
Notes: 1. CE may be delayed up to t
ACC
- tCE after the address transition without impact on t
ACC
.
2. OE may be delayed up to tCE - tOE after the falling edge of CE with out im pa ct on tCE or by t
ACC
- tOE after an address change
without impact on t
ACC
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
Note: 1. This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol Parameter
AT28HC256-70 AT28C2 56-90 AT28HC256-12
UnitsMinMaxMinMaxMinMax
t
ACC
Address to Output Delay 70 90 120 ns
t
CE
(1)
CE to Output Delay 70 90 120 ns
t
OE
(2)
OE to Output Delay 0 35 0 40 0 50 ns
t
DF
(3)(4)
CE or OE to Output Float 0 35 0 40 0 50 ns
t
OH
Output Hold from OE, CE or Address,
whichever occurred first
000ns
t
R
, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C
(1)
Symbol Typ Max Units Conditions
C
IN
46pFV
IN
= 0V
C
OUT
812pFV
OUT
= 0V
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