ATMEL AT28C64B-25PI, AT28C64B-25PC, AT28C64B-25JI, AT28C64B-25JC, AT28C64B-20TI Datasheet
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Features
0270E
Fast Read Access Time - 150 ns
•
Automatic Page Write Operation
•
Internal Address and Data Latches for 64-Bytes
Fast Write Cycle Tim es
•
Page Write Cycle Tim e: 10 ms Ma xi mum
1 to 64-Byte Page Write Opera tio n
Low Power Dissipation
•
40 mA Active Current
100 µA CMOS Standby Current
Hardware and Software Data Protection
•
DATA Polling and Toggl e Bit for End of Write Detec tion
•
High Reliabili ty C MOS Technology
•
Endurance: 100,000 Cycles
Data Retention: 10 Years
Single 5V ± 10% Supply
•
CMOS and TTL Compatible Inputs and Outputs
•
JEDEC Approved Byte-Wid e Pin ou t
•
Commercial and Industrial Temperature Ranges
•
Description
The AT28C64B is a high-performance electrically erasable and programmable read
only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology , the device offers
access times to 150 ns with power dissipation of just 220 mW. W hen the device is
deselected, the CMOS standby current is less than 100 µA.
(continued)
Pin Configurations
Pin Name Function
A0 - A12 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connec t
PDIP, SOIC
Top View
AT28C64B
64K (8K x 8)
CMOS
2
E
PROM with
Page Write and
Software Data
Protection
AT28C64B
PLCC
Top View
Note: PLCC package pins 1 and
17 are DON’T CONNECT.
TSOP
Top View
2-205
Description (Continued)
The AT28C64B is accessed like a Static RAM for the read
or write cycle without the need for external components.
The device contains a 64-byte page register to allow writing of up to 64-bytes simultaneously. During a write cycle,
the addresses and 1 to 64-bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device
will automatically write the latched data using an internal
control timer. The end of a write cycle can be detected by
DATA POLLING of I/O7. Once the end of a write cycle has
been detected, a new access for a read or write can begin.
Block Diagram
Atmel’s AT28C64B has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correc tion for extended endurance and improved
data retention characteristics. An optional software data
protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64-bytes
2
PROM for device identification or tracking.
of E
Absolute Maximum Ratings*
Temperature Under Bias.................-55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
2-206 AT28C64B
+ 0.6V
CC
*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-
mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Device Operation
READ: The AT28C64B is accessed like a Static RAM.
CE and OE are low and WE is high, the data stored
When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the highimpedance state when either
line control gives designers flexibility in preventing bus
contention in their systems.
BYTE WRITE: A low pulse on the
WE low (respectively) and OE high initiates a write cy-
or
cle. The address is latched on the falling edge of
WE, whichever occurs last. The data is latched by the firs t
rising edge of
started, it will automatically time itself to completion. Once
a programming operation has been initiated and for the
duration of t
ing operation.
PAGE WRITE: The page write operation of the
AT28C64B allows 1 to 64-bytes of data to be written into
the device during a single internal programming period. A
page write operation is initiated in the same manner as a
byte write; after the first byte is written, it can then be followed by 1 to 63 additional bytes. Each successive byte
must be loaded within 150 µs (t
If the t
BLC
cepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 to
A12 inputs. For each
page write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page
are to be written. The bytes may be loaded in any order
and may be altered within the same load period. Only
bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
DATA POLLING: The AT28C64B features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complem ent of the written data to be presented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin.
write cycle.
TOGGLE BIT: In addition to
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6
will stop toggling, and valid data will be read. Toggle bit
reading may begin at any time during the write cycle.
CE or WE. Once a byte write has been
, a read operation will effectively be a poll-
WC
limit is exceeded, the AT28C64B will cease ac-
WE high to low transition during the
DATA Polling may begin at any time during the
CE or OE is high. This dual
WE or CE input with CE
CE or
) of the previous byte.
BLC
DATA Polling, the AT28C64B
AT28C64B
DATA PROTECTION: If precautions are not taken, inad-
vertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware
and software features that will protect the memory agains t
inadvertent writes.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent writes to the AT28C64B in the
following ways: (a) V
cal), the write function is inhibited; (b) V
- once V
time out 5 ms (typical) before allowing a write; (c) write
inhibit - holding any one of
inhibits write cycles; (d) noise filter - pulses of less than 15
ns (typical) on the
cycle.
SOFTWARE DATA PROTECTION: A software controlled
data protection feature has been implemented on the
AT28C64B. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C64B is
shipped from Atmel with SDP disabled.
SDP is enabled by the user issuing a series of three write
commands in which three specific bytes of data are written
to three specific addresses (refer to the
has reached 3.8V, the device will automatically
CC
Protection Algorithm
ing the 3-byte command sequence and waiting t
entire AT2 8C64B will be protected against inadvertent
writes. It should be noted that even after SDP is enabled,
the user may still perform a byte or page write to the
AT28C64B b y preceding the data to be written by the
same 3-byte command sequence used to enable SDP.
Once set, SDP remains active unless the disable command sequence is issued. Power transitions do not disable SDP, and SDP protects the AT28C64B during powerup and power-down conditions. All command sequences
must conform to the page write timing specifications. The
data in the enable and disable command sequences is not
actually written into the device; their addresses may still
be written with user data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal
write timers. No data will be written to the device. However, for the duration of t
tively be polling operations.
DEVICE IDENTIFICA TION: An extra 64-bytes of
EEPROM memory are av ailable to the user for device
identification. By raising A9 to 12V ± 0.5V and using address locations 1FC0H to 1FFFH, the additional bytes
may be written to or read from in the same manner as the
regular memory array.
sense - if VCC is below 3.8V (typi-
CC
power-on delay
CC
OE low, CE high, or WE high
WE or CE inputs will not initiate a write
Software Data
diagram in this data sheet). After writ-
, the
WC
, read operations will effec-
WC
2-207
DC and AC Operating Range
AT28C64B-15 AT28C64B-20 AT28C64B-25
Operating
Temperature (Case)
Power Supply 5V ± 10% 5V ± 10% 5V ± 10%
V
CC
Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C
Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C
Operating Modes
Mode CE OE WE I/O
X
V
IL
V
IH
(1)
Read V
(2)
Write
Standby/Write Inhibit V
IL
V
IL
IH
Write Inhibit X X V
Write Inhibit X V
Output Disable X V
Chip Erase V
Notes: 1. X can be V
2. Refer to the
data sheet.
or VIH.
IL
AC Write Waveforms
IL
diagrams in this
IL
IH
(3)
VH
3. VH = 12.0V ± 0.5V.
V
IH
V
IL
X High Z
IH
X
X High Z
VIL High Z
D
D
OUT
IN
DC Characteristics
Symbol Parameter Condition Min Max Units
I
LI
I
LO
I
SB1
I
SB2
I
CC
V
IL
V
IH
V
OL
V
OH
2-208 AT28C64B
Input Load Current VIN = 0V to VCC + 1V 10 µA
Output Leakage Current V
VCC Standby Current CMOS CE = V
= 0V to V
I/O
CC
CC
10 µA
- 0.3V to VCC + 1V Com., Ind. 100 µA
VCC Standby Current TTL CE = 2.0V to VCC + 1V 2 mA
V
Active Current f = 5 MHz; I
CC
= 0 mA 40 mA
OUT
Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA .40 V
Output High Voltage IOH = -400 µA 2.4 V
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