Datasheet AT28C64B Datasheet (ATMEL)

Features

• Fast Read Access Time – 150 ns

• Automatic Page Write Operation

– Internal Address and Data Latches for 64 Bytes

• Fast Write Cycle Times

– Page Write Cycle Time: 10 ms Maximum (Standard)

2 ms Maximum (Option)

– 1 to 64-byte Page Write Operation

• Low Power Dissipation

– 40 mA Active Current
–100 µA CMOS Standby Current

• Hardware and Software Data Protection

• DATA Polling and Toggle Bit for End of Write Detection

• High Reliability CMOS Technology

– Endurance: 100,000 Cycles
– Data Retention: 10 Years

• Single 5V ±10% Supply

• CMOS and TTL Compatible Inputs and Outputs

• JEDEC Approved Byte-wide Pinout

• Commercial and Industrial Temperature Ranges

• Green (Pb/Halide-free) Packaging Option

1. Description

The AT28C64B is a high-performance electrically-erasable and programmable read­only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 150 ns with power dissipation of just 220 mW. When the device is
deselected, the CMOS standby current is less than 100 µA.

64K (8K x 8)
Parallel
EEPROM with
Page Write and
Software Data
Protection

AT28C64B

The AT28C64B is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
64 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA
detected, a new access for a read or write can begin.

Atmel’s AT28C64B has additional features to ensure high quality and manufacturabil­ity. The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra
64 bytes of EEPROM for device identification or tracking.

POLLING of I/O7. Once the end of a write cycle has been

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2. Pin Configurations

Pin Name Function

A0 - A12 Addresses

CE

Chip Enable

OE

WE

Output Enable

Write Enable

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

DC Don’t Connect

2.1 28-lead PDIP, 28-lead SOIC Top View

NC

A12

A7
A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1
I/O2

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28

VCC

27

WE

26

NC

25

A8

24

A9

23

A11

22

OE

21

A10

20

CE

19

I/O7

18

I/O6

17

I/O5

16

I/O4

15

I/O3

2.3 28-lead TSOP Top View

1

OE

2

A11

3

A9

4

A8

5

NC

6

WE

NC

A12

A7
A6
A5
A4
A3

7
8
9
10
11
12
13
14

VCC

28
27
26
25
24
23
22
21
20
19
18
17
16
15

A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2

2.2 32-lead PLCC Top View

A7

A12NCDC

432

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12

NC

13

I/O0

14151617181920

I/O1

I/O2

Note: PLCC package pins 1 and 17 are Don’t Connect.

2

AT28C64B

GND

VCCWENC

1

323130

DC

I/O3

I/O4

29
28
27
26
25
24
23
22
21

I/O5

A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6

0270J–PEEPR–04/05

3. Block Diagram

AT28C64B

4. Device Operation

4.1 Read

The AT28C64B is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high-impedance state when either CE
control gives designers flexibility in preventing bus contention in their systems.

4.2 Byte Write

A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a
write cycle. The address is latched on the falling edge of CE
The data is latched by the first rising edge of CE
will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of t

VCC

GND

OE

WE

CE

ADDRESS

INPUTS

DATA INPUTS/OUTPUTS

I/O0 - I/O7

OE, CE and WE

LOGIC

Y DECODER

X DECODER

DATA LATCH

INPUT/OUTPUT

BUFFERS

Y-GATING

CELL MATRIX

IDENTIFICATION

or OE is high. This dual line

or WE, whichever occurs last.

or WE. Once a byte write has been started, it

, a read operation will effectively be a polling operation.

WC

4.3 Page Write

0270J–PEEPR–04/05

The page write operation of the AT28C64B allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63
additional bytes. Each successive byte must be loaded within 150 µs (t
byte. If the t

limit is exceeded, the AT28C64B will cease accepting data and commence the

BLC

) of the previous

BLC

internal programming operation. All bytes during a page write operation must reside on the
same page as defined by the state of the A6 to A12 inputs. For each WE

high to low transition

during the page write operation, A6 to A12 must be the same.

The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are
specified for writing will be written; unnecessary cycling of other bytes within the page does
not occur.

3

4.4 DATA Polling

The AT28C64B features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is
valid on all outputs, and the next write cycle may begin. DATA
during the write cycle.

4.5 Toggle Bit

In addition to DATA Polling, the AT28C64B provides another method for determining the end of
a write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog­gling, and valid data will be read. Toggle bit reading may begin at any time during the write
cycle.

4.6 Data Protection

If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel has incorporated both hardware and software features that will protect
the memory against inadvertent writes.

4.6.1 Hardware Data Protection

Hardware features protect against inadvertent writes to the AT28C64B in the following ways:
(a) V
delay – once V
before allowing a write; (c) write inhibit – holding any one of OE
inhibits write cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE
inputs will not initiate a write cycle.

sense – if VCC is below 3.8 V (typical), the write function is inhibited; (b) VCC power-on

CC

Polling may begin at any time

has reached 3.8 V, the device will automatically time out 5 ms (typical)

CC

low, CE high, or WE high

or CE

4.6.2 Software Data Protection

A software controlled data protection feature has been implemented on the AT28C64B. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C64B is shipped from Atmel with SDP dis­abled.

SDP is enabled by the user issuing a series of three write commands in which three specific
bytes of data are written to three specific addresses (see “Software Data Protection Algo­rithms” on page 10). After writing the 3-byte command sequence and waiting t
AT28C64B will be protected against inadvertent writes. It should be noted that even after SDP
is enabled, the user may still perform a byte or page write to the AT28C64B by preceding the
data to be written by the same 3-byte command sequence used to enable SDP.

Once set, SDP remains active unless the disable command sequence is issued. Power transi­tions do not disable SDP, and SDP protects the AT28C64B during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not actually written into the device;
their addresses may still be written with user data in either a byte or page write operation.

After setting SDP, any attempt to write to the device without the 3-byte command sequence
will start the internal write timers. No data will be written to the device. However, for the dura­tion of t

4.7 Device Identification

An extra 64 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V ±0.5V and using address locations 1FC0H to 1FFFH, the additional bytes
may be written to or read from in the same manner as the regular memory array.

, read operations will effectively be polling operations.

WC

, the entire

WC

4

AT28C64B

0270J–PEEPR–04/05

AT28C64B

5. DC and AC Operating Range

AT28C64B-15 AT28C64B-20 AT28C64B-25

Operating
Temperature (Case)

VCC Power Supply 5V ±10% 5V ±10% 5V ±10%

6. Operating Modes

Mode CE OE WE I/O

Read V

(2)

Write

Standby/Write Inhibit V

Write Inhibit X X V

Write Inhibit X V

Output Disable X V

Chip Erase V

Notes: 1. X can be VIL or VIH.

2. See “AC Write Waveforms” on page 8.

3. VH = 12.0V ±0.5V.

Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C

Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C

V

X

V

IL

V

IH

(1)

IL

IH

(3)

H

IL

V

IL

IH

IL

V

IH

V

IL

X High Z

IH

X

X High Z

VIL High Z

D

OUT

D

IN

7. Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

+ 0.6V

CC

Voltage on OE and A9

with Respect to Ground...................................-0.6V to +13.5V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability

8. DC Characteristics

Symbol Parameter Condition Min Max Units

I

I

I

I

I

V

V

V

V

LI

LO

SB1

SB2

CC

IL

IH

OL

OH

Input Load Current VIN = 0V to VCC + 1V 10 µA

Output Leakage Current V

VCC Standby Current CMOS CE = V

= 0V to V

I/O

CC

- 0.3V to VCC + 1V Com., Ind. 100 µA

CC

10 µA

VCC Standby Current TTL CE = 2.0V to VCC + 1V 2 mA

V

Active Current f = 5 MHz; I

CC

= 0 mA 40 mA

OUT

Input Low Voltage 0.8 V

Input High Voltage 2.0 V

Output Low Voltage IOL = 2.1 mA 0.40 V

Output High Voltage IOH = -400 µA 2.4 V

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5

9. AC Read Characteristics

Symbol Parameter

AT28C64B-15 AT28C64B-20 AT28C64B-25

UnitsMin Max Min Max Min Max

t

t

t

t

t

ACC

CE

OE

DF

OH

(1)

(2)

(3)(4)

Address to Output Delay 150 200 250 ns

CE to Output Delay 150 200 250 ns

OE to Output Delay 0 70 0 80 0 100 ns

CE or OE to Output Float 0 50 0 55 0 60 ns

Output Hold from OE, CE or
Address, whichever occurred first

10. AC Read Waveforms

ADDRESS

CE

OE

OUTPUT

(1)(2)(3)(4)

000ns

ADDRESS VALID

t

CE

t

OE

t

DF

t

OH

t

ACC

HIGH Z

OUTPUT VALID

Notes: 1. CE may be delayed up to t

2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by t
without impact on t

is specified from OE or CE whichever occurs first (CL = 5 pF).

3. t

DF

ACC

.

4. This parameter is characterized and is not 100% tested.

- tCE after the address transition without impact on t

ACC

ACC

.

- tOE after an address change

ACC

6

AT28C64B

0270J–PEEPR–04/05

11. Input Test Waveforms and Measurement Level

, tF < 5 ns

t

R

12. Output Test Load

AT28C64B

13. Pin Capacitance

f = 1 MHz, T = 25°C

Symbol Typ Max Units Conditions

C

IN

C

OUT

Note: 1. This parameter is characterized and is not 100% tested.

(1)

46pFV

812pFV

IN

OUT

= 0V

= 0V

0270J–PEEPR–04/05

7

14. AC Write Characteristics

Symbol Parameter Min Max Units

t

, t

AS

OES

t

AH

t

CS

t

CH

t

WP

t

DS

t

, t

DH

OEH

Address, OE Setup Time 0 ns

Address Hold Time 50 ns

Chip Select Setup Time 0 ns

Chip Select Hold Time 0 ns

Write Pulse Width (WE or CE) 100 ns

Data Setup Time 50 ns

Data, OE Hold Time 0 ns

15. AC Write Waveforms

15.1 WE Controlled

t

OE

ADDRESS

CE

OES

t

AS

t

OEH

t

t

AH

CH

15.2 CE

WE

DATA IN

Controlled

OE

ADDRESS

WE

CE

DATA IN

t

CS

t

WP

t

DS

t

OES

t

AS

t

CS

t

AH

t

WP

t

DS

t

t

OEH

CH

t

DH

t

DH

8

AT28C64B

0270J–PEEPR–04/05

AT28C64B

16. Page Mode Characteristics

Symbol Parameter Min Max Units

t

WC

t

WC

t

AS

t

AH

t

DS

t

DH

t

WP

t

BLC

t

WPH

Write Cycle Time 10 ms

Write Cycle Time (option available; contact Atmel sales office for
ordering part number)

Address Setup Time 0 ns

Address Hold Time 50 ns

Data Setup Time 50 ns

Data Hold Time 0 ns

Write Pulse Width 100 ns

Byte Load Cycle Time 150 µs

Write Pulse Width High 50 ns

17. Page Mode Write Waveforms

OE

CE

t

WP

WE

A0 -A12

DATA

t

AS

VALID ADD

VALID DATA

t

AH

t

DS

(1)(2)

t

DH

t

WPH

2ms

t

BLC

t

WC

Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE).

must be high only when WE and CE are both low.

2. OE

18. Chip Erase Waveforms

tS = tH = 1 µs (min.)
tW = 10 ms (min.)
VH = 12.0V ±0.5V

t

S

t

W

t

H

0270J–PEEPR–04/05

9

19. Software Data Protection Enable
Algorithm

(1)

LOAD DATA AA

TO

ADDRESS 1555

20. Software Data Protection Disable
Algorithm

(1)

LOAD DATA AA

TO

ADDRESS 1555

LOAD DATA 55

TO

ADDRESS 0AAA

LOAD DATA A0

TO

ADDRESS 1555

LOAD DATA XX

TO

ANY ADDRESS

LOAD LAST BYTE

TO

LAST ADDRESS

WRITES ENABLED

(4)

ENTER DATA
PROTECT STATE

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A12 - A0 (Hex).

2. Write Protect state will be activated at end of write
even if no other data is loaded.

3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.

4. 1 to 64 bytes of data are loaded.

LOAD DATA 55

TO

ADDRESS 0AAA

LOAD DATA 80

(2)

TO

ADDRESS 1555

LOAD DATA AA

TO

ADDRESS 1555

LOAD DATA 55

TO

ADDRESS 0AAA

LOAD DATA 20

TO

ADDRESS 1555

LOAD DATA XX

TO

ANY ADDRESS

LOAD LAST BYTE

TO

LAST ADDRESS

EXIT DATA
PROTECT STATE

(4)

(3)

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A12 - A0 (Hex).

2. Write Protect state will be activated at end of write
even if no other data is loaded.

3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.

4. 1 to 64 bytes of data are loaded.

21. Software Protected Write Cycle Waveforms

OE

CE

WE

A0 -A5

A6 - A12

DATA

t

WP

t

AS

t

AH

t

DS

t

DH

t

WPH

(1)(2)

t

BLC

t

WC

Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the software

code has been entered.

must be high only when WE and CE are both low.

2. OE

10

AT28C64B

0270J–PEEPR–04/05

AT28C64B

22. Data Polling Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

WR

Data Hold Time 0 ns

OE Hold Time 0 ns

OE to Output Delay

(1)

Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested. See “AC Read Characteristics” on page 6.

23. Data Polling Waveforms

t

OEH

t

DH

t

OE

t

WR

ns

24. Toggle Bit Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

OEHP

t

WR

Data Hold Time 10 ns

OE Hold Time 10 ns

OE to Output Delay

(2)

OE High Pulse 150 ns

Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See “AC Read Characteristics” on page 6.

t

OEH

(1)(2)(3)

t

DH

t

OEHP

t

OE

t

WR

25. Toggle Bit Waveforms

ns

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

0270J–PEEPR–04/05

11

26. Normalized ICC Graphs

12

AT28C64B

0270J–PEEPR–04/05

AT28C64B

27. Ordering Information

27.1 Standard Package

I

t

ACC

(ns)

150 40 0.1

200 40 0.1

250 40 0.1

CC

(mA)

(1)

Ordering Code Package Operation RangeActive Standby

AT28C64B-15JC
AT28C64B-15PC
AT28C64B-15SC
AT28C64B-15TC

AT28C64B-15JI
AT28C64B-15PI
AT28C64B-15SI
AT28C64B-15TI

AT28C64B-20JC
AT28C64B-20PC
AT28C64B-20SC
AT28C64B-20TC

AT28C64B-20JI
AT28C64B-20PI
AT28C64B-20SI
AT28C64B-20TI

AT28C64B-25JC
AT28C64B-25PC
AT28C64B-25SC
AT28C64B-25TC

AT28C64B-25JI
AT28C64B-25PI
AT28C64B-25SI
AT28C64B-25TI

32J

28P6

28S
28T

32J

28P6

28S
28T

32J

28P6

28S
28T

32J

28P6

28S
28T

32J

28P6

28S
28T

32J

28P6

28S
28T

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Note: 1. See “Valid Part Numbers” on page 14.

27.2 Green Package Option (Pb/Halide-free)

I

t

ACC

(ns)

150 40 0.1

32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)

28P6 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)

28T 28-lead, Plastic Thin Small Outline Package (TSOP)

W Die

0270J–PEEPR–04/05

CC

(mA)

Ordering Code Package Operation RangeActive Standby

AT28C64B-15JU
AT28C64B-15SU
AT28C64B-15TU

Package Type

32J
28S
28T

Industrial

(-40°C to 85°C)

13

28. Valid Part Numbers

The following table lists standard Atmel products that can be ordered.

Device Numbers Speed Package and Temperature Combinations

AT28C64B 15 JC, JI, JU, PC, PI, SC, SI, SU, TC, TI, TU

AT28C64B 20 JC, JI, PC, PI, SC, SI, TC, TI

AT28C64B 25 JC, JI, PC, PI, SC, SI, TC, TI

AT28C64B –W

29. Die Products

Reference Section: Parallel EEPROM Die Products

14

AT28C64B

0270J–PEEPR–04/05

30. Packaging Information

30.1 32J – PLCC

AT28C64B

1.14(0.045) X 45˚

B

e

0.51(0.020)MAX

45˚ MAX (3X)

Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.

2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.

3. Lead coplanarity is 0.004" (0.102 mm) maximum.

PIN NO. 1
IDENTIFIER

D1

D

D2

1.14(0.045) X 45˚

E1 E

0.318(0.0125)

0.191(0.0075)

E2

B1

A2

A1

A

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A 3.175 – 3.556

A1 1.524 – 2.413

A2 0.381 – –

D 12.319 – 12.573

D1 11.354 – 11.506 Note 2

D2 9.906 – 10.922

E 14.859 – 15.113

E1 13.894 – 14.046 Note 2

E2 12.471 – 13.487

B 0.660 – 0.813

B1 0.330 – 0.533

e 1.270 TYP

MIN

NOM

MAX

NOTE

10/04/01

2325 Orchard Parkway

R

San Jose, CA 95131

0270J–PEEPR–04/05

TITLE

32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)

DRAWING NO.

32J

REV.

B

15

30.2 28P6 – PDIP

PIN

1

E1

A1

B

REF

E

B1

C

L

SEATING PLANE

A

e

D

0º ~ 15º

eB

Notes: 1. This package conforms to JEDEC reference MS-011, Variation AB.

2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

TITLE

2325 Orchard Parkway

R

San Jose, CA 95131

28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A – – 4.826

A1 0.381 – –

D 36.703 – 37.338 Note 2

E 15.240 – 15.875

E1 13.462 – 13.970 Note 2

B 0.356 – 0.559

B1 1.041 – 1.651

L 3.048 – 3.556

C 0.203 – 0.381

eB 15.494 – 17.526

e 2.540 TYP

MIN

NOM

MAX

DRAWING NO.

28P6

NOTE

09/28/01

REV.

B

16

AT28C64B

0270J–PEEPR–04/05

30.3 28S – SOIC

Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.

AT28C64B

0.51(0.020)

0.33(0.013)

PIN 1

TOP VIEW

18.10(0.7125)

17.70(0.6969)

0.30(0.0118)

0.10(0.0040)

0º ~ 8º

7.60(0.2992)

7.40(0.2914)

1.27(0.50) BSC

1.27(0.050)

0.40(0.016)

10.65(0.419)

10.00(0.394)

2.65(0.1043)

2.35(0.0926)

SIDE VIEWS

0.32(0.0125)

0.23(0.0091)

2325 Orchard Parkway

R

San Jose, CA 95131

0270J–PEEPR–04/05

TITLE

28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC)

JEDEC Standard MS-013

DRAWING NO.

28S

8/4/03

REV.

B

17

30.4 28T – TSOP

PIN 1

Pin 1 Identifier Area

D1

D

e

E

b

A2

A

A1

Notes: 1. This package conforms to JEDEC reference MO-183.

2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

0º ~ 5º

SEATING PLANE

SYMBOL

c

L

L1

GAGE PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

A – – 1.20

A1 0.05 – 0.15

A2 0.90 1.00 1.05

D 13.20 13.40 13.60

D1 11.70 11.80 11.90 Note 2

E 7.90 8.00 8.10 Note 2

L 0.50 0.60 0.70

L1 0.25 BASIC

b 0.17 0.22 0.27

c 0.10 – 0.21

e 0.55 BASIC

NOM

MAX

NOTE

18

2325 Orchard Parkway

R

San Jose, CA 95131

AT28C64B

TITLE

28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline

Package, Type I (TSOP)

DRAWING NO.

28T

0270J–PEEPR–04/05

12/06/02

REV.

C

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0270J–PEEPR–04/05