ATMEL AT28C256F-25UM-883, AT28C256F-25TI, AT28C256F-25TC, AT28C256F-25SI, AT28C256F-25SC Datasheet
...
AT28C256
256K (32K x 8)
Paged
CMOS
E2PROM
Features
•
Fast Read Access Time - 150 ns
•
Automatic Page Write Operation
Internal Address and Data Latches for 64-Bytes
Internal Control Timer
•
Fast Write Cycle Times
Page Write Cycle Tim e: 3 ms or 1 0 ms Maxim um
1 to 64-Byte Page Write Operation
•
Low Power Dissipation
50 mA Active Current
200 µA CMOS Standby Current
•
Hardware and Software Data Protection
•
DATA Polling for End of Write Detection
•
High Reliabili ty C MOS Technology
Endurance: 104 or 105 Cycles
Data Retention: 10 Years
•
Single 5V ± 10% Supply
•
CMOS and TTL Compatible Inputs and Outputs
•
JEDEC Approved Byte-Wide Pinout
•
Full Military, Commercial, and Industrial Temperature Ranges
Description
The AT28C256 is a high-performance Electrically Erasable and Programmable Read
Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access
times to 150 ns with power dissipation of just 440 mW. When the device is deselected,
the CMOS standby current is less than 200 µA.
(continued)
LCC, PLCC
Top View
Pin Name Function
A0 - A14 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
I/O0 - I/O7 Data Input s /O utput s
NC No Connect
DC Don’t Connect
Pin Configurations
TSOP
Top View
PGA
Top View
Note: PLCC package pins 1 and
17 are DON’T CONNECT.
CERDIP, PDIP,
FLATPACK, SOIC
Top View
0006F
AT28C256
2-217
Block Diagram
The AT28C256 is accessed like a Static RAM for the read
or write cycle without the need for external components.
The device contains a 64-byte page register to allow writing of up to 64-bytes simultaneously. During a write cycle,
the addresses and 1 to 64-bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device
will automatically write the latched data using an internal
control timer. The end of a write cycle can be detected by
DATA POLLING of I/O7. Once the end of a write cycle has
been detected a new access for a read or write can begin.
Atmel’s 28C256 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correc tion for extended endurance and improved
data retention characteristics. An optional software data
protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64-bytes
of E
2
PROM for device identification or tracking.
Description (Continued)
Temperature Under Bias.................-55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed unde r “Abso lute Maxi-
mum Ratings” may cause permanent da ma ge to th e devi ce .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Absolute Maximum Ratings*
2-218 AT28C256
Device Operation
READ: The AT28C256 is accessed like a Static RAM.
When
CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either
CE or OE is high. This dualline control gives designers flexibility in preventing bus
contention in their system.
BYTE WRITE: A low pulse on the
WE or CE input with CE
or
WE low (respectively) and OE high initiates a write cy-
cle. The address is latched on the falling edge of
CE or
WE, whichever occurs last. The data is latched by the firs t
rising edge of
CE or WE. Once a byte write has been
started it will automatically time itself to completion. Once
a programming operation has been initiated and for the
duration of t
WC
, a read operation will effectively be a poll-
ing operation.
PAGE WRITE: The page write operation of the AT28C256
allows 1 to 64-bytes of data to be written into the device
during a single internal programming period. A page write
operation is initiated in the same manner as a byte write;
the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within
150 µs (t
BLC
) of the previous byte. If the t
BLC
limit is exceeded the AT28C256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page
as defined by the state of the A6 - A14 inputs. For each
WE high to low transition during the page write operation,
A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
DATA POLLING: The AT28C256 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complem ent of the written data to be presented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin.
DATA Polling may begin at anytime during the
write cycle.
TOGGLE BIT: In addition to
DATA Polling the AT28C256
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
(continued)
DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28C256 in the following ways: (a) V
CC
sense - if VCC is below 3.8V (typical) the
write function is inhibited; (b) V
CC
power-on delay - once
V
CC
has reached 3.8V the device will automatically time
out 5 ms (typical) before allowing a write: (c) write inhibit holding any one of
OE low, CE high or WE high inhibits
write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software controlled
data protection feature has been implemented on the
AT28C256. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C256 is
shipped from Atmel with SDP disabled.
SDP is enabled by the h ost system issuing a series of
three write co mmands; three specific bytes of data are
written to three specific addresses (refer to Software Data
Protection Algorithm). After writing the 3-byte command
sequence and after t
WC
the entire AT28C256 will be protected against inadvertent write operations. It should be
noted, that o nce protected the host may sti ll perform a
byte or page write to the AT28C256. This is done by preceding the data to be written by the same 3-byte command
sequence used to enable SDP.
Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will pr otect the AT28C256 during
power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in
either a byte or page write operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of t
WC
, read operations will effectively be
polling operations.
AT28C256
2-219
Symbol Parameter Condition Min Max Units
I
LI
Input Load Current VIN = 0V to VCC + 1V 10 µA
I
LO
Output Leakage Current V
I/O
= 0V to V
CC
10 µA
I
SB1
VCC Standby Current CMOS CE = V
CC
- 0.3V to VCC + 1V
Com., Ind. 200 µA
Mil. 300 µA
I
SB2
VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA
I
CC
V
CC
Active Current f = 5 MHz; I
OUT
= 0 mA 50 mA
V
IL
Input Low Voltage 0.8 V
V
IH
Input High Voltage 2.0 V
V
OL
Output Low Voltage IOL = 2.1 mA .45 V
V
OH
Output High Voltage IOH = -400 µA 2.4 V
DC Characteristics
AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35
Operating
Temperature (Case)
Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C
Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C
Mil. -55°C - 125°C -55°C - 125°C -55°C - 125°C -55°C - 125°C
V
CC
Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%
DC and AC Operating Range
Mode CE OE WE I/O
Read V
IL
V
IL
V
IH
D
OUT
Write
(2)
V
IL
V
IH
V
IL
D
IN
Standby/Write Inhibit V
IH
X
(1)
X High Z
Write Inhibit X X V
IH
Write Inhibit X V
IL
X
Output Disable X V
IH
X High Z
Chip Erase V
IL
VH
(3)
VIL High Z
3. VH = 12.0V ± 0.5V.
Notes: 1. X can be V
IL
or VIH.
2. Refer to AC Programming Waveforms.
Operating Modes
DEVICE IDENTIFICATION: An extra 64-bytes of
E
2
PROM memory are available to the user for device
identification. By raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may
be written to or read from in the same manner as the regular memory array.
OPTIONAL CHIP ERASE MODE: The entire device can
be erased using a 6-byte software code. Please see Software Chip Erase application note for details.
Device Operation (Continued)
2-220 AT28C256
AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35
Symbol Parameter
Min Max Min Max Min Max Min Max
Units
t
ACC
Address to Output Delay 150 200 250 350 ns
t
CE
(1)
CE to Output Delay 150 200 250 350 ns
t
OE
(2)
OE to Output Delay 0 70 0 80 0 100 0 100 ns
t
DF
(3, 4)
CE or OE to Output Float 0 50 0 55 0 60 0 70 ns
t
OH
Output Hold from OE, CE or
Address, whichever
occurred first
0000ns
AC Read Characteristics
Notes: 1. CE may be delayed up to t
ACC
- tCE after the ad dress
transition without impact on t
ACC
.
2.
OE may be delayed up to tCE - tOE after the falling
edge of
CE without impact on tCE or by t
ACC
- tOE
after an address change without impact on t
ACC
.
3. tDF is specified from OE or CE whichever occu r s first
(C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
AC Read Waveforms
(1, 2, 3, 4)
tR, tF < 5ns
Input Test Waveforms and
Measurement Level
Output Test Load
Typ Max Units Conditions
C
IN
46pFV
IN
= 0V
C
OUT
812pFV
OUT
= 0V
Pin Capacitance (f = 1 MHz, T = 25°C)
(1)
Note: 1. This parameter is characterized and is not 100% tested.
AT28C256
2-221
Loading...