ATMEL AT28C256 User Manual

Features

Fast Read Access Time – 150 ns
Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes – Internal Control Timer
Fast Write Cycle Times
– Page Write Cycle Time: 3 ms or 10 ms Maximum – 1 to 64-byte Page Write Operation
– 50 mA Active Current –200 µA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
– Endurance: 104 or 105 Cycles – Data Retention: 10 Years
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
Full Military, Commercial, and Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Option
256K (32K x 8) Paged Parallel EEPROM
AT28C256

1. Description

The AT28C256 is a high-performance electrically erasable and programmable read­only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac­tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 200 µA.
The AT28C256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA new access for a read or write can begin.
Atmel’s AT28C256 has additional features to ensure high quality and manufacturabil­ity. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking.
Polling of I/O7. Once the end of a write cycle has been detected a
0006I–PEEPR–4/05

2. Pin Configurations

Pin Name Function
A0 - A14 Addresses
CE
Chip Enable
OE
WE
Output Enable
Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect

2.1 28-lead TSOP Top View

1
OE
A11
A9 A8
A13
WE
VCC
A14 A12
A7 A6 A5 A4 A3
2 3 4 5 6 7 8 9 10 11 12 13 14
28
A10
27
CE
26
I/O7
25
I/O6
24
I/O5
23
I/O4
22
I/O3
21
GND
20
I/O2
19
I/O1
18
I/O0
17
A0
16
A1
15
A2

2.3 32-pad LCC, 28-lead PLCC Top View

A7
A12
A14DCVCCWEA13
A6 A5 A4 A3 A2 A1 A0
NC
I/O0
432
5 6 7 8 9 10 11 12 13
14151617181920
I/O1
I/O2
GND
1
DC
323130
I/O3
I/O4
29 28 27 26 25 24 23 22 21
I/O5
A8 A9 A11 NC OE A10 CE I/O7 I/O6

2.2 28-lead PGA Top View

2
AT28C256
Note: PLCC package pins 1 and 17 are Don’t Connect.
2.4 28-lead Cerdip/PDIP/Flatpack/SOIC – Top View
A14 A12
A7 A6 A5 A4 A3 A2 A1
A0 I/O0 I/O1 I/O2
GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28
VCC
27
WE
26
A13
25
A8
24
A9
23
A11
22
OE
21
A10
20
CE
19
I/O7
18
I/O6
17
I/O5
16
I/O4
15
I/O3
0006I–PEEPR–4/05

3. Block Diagram

4. Device Operation

4.1 Read

The AT28C256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE control gives designers flexibility in preventing bus contention in their system.
AT28C256
or OE is high. This dual-line

4.2 Byte Write

4.3 Page Write

4.4 DATA Polling

A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE latched by the first rising edge of CE cally time itself to completion. Once a programming operation has been initiated and for the duration of t
The page write operation of the AT28C256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs (t limit is exceeded the AT28C256 will cease accepting data and commence the internal program­ming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. For each WE write operation, A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
The AT28C256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA cycle.
, a read operation will effectively be a polling operation.
WC
or WE. Once a byte write has been started it will automati-
or WE, whichever occurs last. The data is
) of the previous byte. If the t
BLC
high to low transition during the page
Polling may begin at anytime during the write
BLC
0006I–PEEPR–4/05
3

4.5 Toggle Bit

In addition to DATA Polling the AT28C256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog­gling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.

4.6 Data Protection

If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes.

4.6.1 Hardware Protection

Hardware features protect against inadvertent writes to the AT28C256 in the following ways: (a) V
sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay –
CC
once V a write; (c) write inhibit – holding any one of OE and (d) noise filter – pulses of less than 15 ns (typical) on the WE write cycle.

4.6.2 Software Data Protection

A software controlled data protection feature has been implemented on the AT28C256. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C256 is shipped from Atmel with SDP disabled.
CC
has reached 3.8V the device will automatically time out 5 ms (typical) before allowing
low, CE high or WE high inhibits write cycles;
or CE inputs will not initiate a
SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to “Software Data Protection” algo­rithm). After writing the 3-byte command sequence and after t protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28C256. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP.
Once set, SDP will remain active unless the disable command sequence is issued. Power transi­tions do not disable SDP and SDP will protect the AT28C256 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of
, read operations will effectively be polling operations.
t
WC

4.7 Device Identification

An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais­ing A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array.
the entire AT28C256 will be
WC

4.8 Optional Chip Erase Mode

The entire device can be erased using a 6-byte software code. Please see “Software Chip Erase” application note for details.
4
AT28C256
0006I–PEEPR–4/05
AT28C256

5. DC and AC Operating Range

AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35
Operating Temperature (Case)
Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%
V
CC

6. Operating Modes

Mode CE OE WE I/O
Read V
(2)
Write
Standby/Write Inhibit V
Write Inhibit X X V
Write Inhibit X V
Output Disable X V
Chip Erase V
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
= 12.0V ± 0.5V.
3. V
H
Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C
Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C
Mil. -55°C - 125°C -55°C - 125°C -55°C - 125°C -55°C - 125°C
IL
V
IL
IH
IL
V
IL
V
IH
(1)
X
IL
IH
(3)
V
H
V
IH
V
IL
X High Z
IH
X
X High Z
V
IL
High Z
D
OUT
D
IN

7. Absolute Maximum Ratings*

Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to V
Voltage on OE
and A9
+ 0.6V
CC
with Respect to Ground...................................-0.6V to +13.5V
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

8. DC Characteristics

Symbol Parameter Condition Min Max Units
I
I
I
I
I
V
V
V
V
LI
LO
SB1
SB2
CC
IL
IH
OL
OH
Input Load Current VIN = 0V to VCC + 1V 10 µA
Output Leakage Current V
VCC Standby Current CMOS CE = V
= 0V to V
I/O
CC
CC
- 0.3V to VCC + 1V
10 µA
Com., Ind. 200 µA
Mil. 300 µA
VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA
V
Active Current f = 5 MHz; I
CC
= 0 mA 50 mA
OUT
Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA 0.45 V
Output High Voltage IOH = -400 µA 2.4 V
0006I–PEEPR–4/05
5

9. AC Read Characteristics

Symbol Parameter
AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35
UnitsMin Max Min Max Min Max Min Max
t
t
t
t
ACC
CE
OE
DF
(1)
(2)
(3)(4)
Address to Output Delay 150 200 250 350 ns
CE to Output Delay 150 200 250 350 ns
OE to Output Delay 0 70 0 80 0 100 0 100 ns
CE or OE to Output Float 050055060070 ns
Output Hold from OE, CE or
t
OH
Address, whichever occurred first
10. AC Read Waveforms
0000 ns
(1)(2)(3)(4)
Notes: 1. CE may be delayed up to t
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by t without impact on t
is specified from OE or CE whichever occurs first (CL = 5 pF).
3. t
DF
ACC
.
4. This parameter is characterized and is not 100% tested.
- tCE after the address transition without impact on t
ACC
ACC
.
- tOE after an address change
ACC
6
AT28C256
0006I–PEEPR–4/05

11. Input Test Waveforms and Measurement Level

tR, tF < 5 ns

12. Output Test Load

13. Pin Capacitance

f = 1 MHz, T = 25°C
(1)
AT28C256
Symbol Typ Max Units Conditions
C
IN
C
OUT
Note: 1. This parameter is characterized and is not 100% tested.
46pFV
812pFV
IN
OUT
= 0V
= 0V
0006I–PEEPR–4/05
7

14. AC Write Characteristics

Symbol Parameter Min Max Units
tAS, t
OES
t
AH
t
CS
t
CH
t
WP
t
DS
tDH, t
OEH
t
DV
Note: 1. NR = No Restriction
Address, OE Setup Time 0 ns
Address Hold Time 50 ns
Chip Select Setup Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE) 100 ns
Data Setup Time 50 ns
Data, OE Hold Time 0 ns
Time to Data Valid NR
(1)

15. AC Write Waveforms

15.1 WE Controlled

15.2 CE
8
AT28C256
Controlled
0006I–PEEPR–4/05
AT28C256

16. Page Mode Characteristics

Symbol Parameter Min Max Units
t
WC
Write Cycle Time (option available)
AT28C256 10 ms
AT28C256F 3 ms
t
AS
t
AH
t
DS
t
DH
t
WP
t
BLC
t
WPH
Address Setup Time 0 ns
Address Hold Time 50 ns
Data Setup Time 50 ns
Data Hold Time 0 ns
Write Pulse Width 100 ns
Byte Load Cycle Time 150 µs
Write Pulse Width High 50 ns
17. Page Mode Write Waveforms
(1)(2)
Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE).
must be high only when WE and CE are both low.
2. OE

18. Chip Erase Waveforms

tS = tH = 5 µsec (min.)
= 10 msec (min.)
t
W
V
= 12.0V ± 0.5V
H
0006I–PEEPR–4/05
9
19. Software Data Protection Enable Algorithm
LOAD DATA AA
TO
ADDRESS 5555
(1)
20. Software Data Protection Disable Algorithm
LOAD DATA AA
TO
ADDRESS 5555
(1)
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS
LOAD LAST BYTE
TO
LAST ADDRESS
WRITES ENABLED
(4)
ENTER DATA PROTECT STATE
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other data is loaded.
3. Write Protect state will be deactivated at end of write period even if no other data is loaded.
4. 1 to 64 bytes of data are loaded.
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
(2)
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS
LOAD LAST BYTE
TO
LAST ADDRESS
EXIT DATA PROTECT STATE
(4)
(3)
21. Software Protected Write Cycle Waveforms
(1)(2)
Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software
code has been entered.
2. OE
must be high only when WE and CE are both low.
10
AT28C256
0006I–PEEPR–4/05
AT28C256
22. Data Polling Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
WR
Data Hold Time 0 ns
OE Hold Time 0 ns
OE to Output Delay
(2)
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See“AC Read Characteristics” on page 6.

23. Data Polling Waveforms

ns
24. Toggle Bit Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
OEHP
t
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
OE High Pulse 150 ns
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics” on page 6.
25. Toggle Bit Waveforms
(1)(2)(3)
ns
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
0006I–PEEPR–4/05
11

26. Normalized ICC Graphs

12
AT28C256
0006I–PEEPR–4/05
AT28C256
27. Ordering Information
(2)

27.1 Standard Package

I
t
ACC
(ns)
150 50 0.2 AT28C256(E,F)-15JC
200 50 0.2 AT28C256(E,F)-20JC
(mA)
CC
Ordering Code Package Operation RangeActive Standby
AT28C256(E,F)-15PC AT28C256(E,F)-15SC AT28C256(E,F)-15TC
AT28C256(E,F)-15JI AT28C256(E,F)-15PI AT28C256(E,F)-15SI AT28C256(E,F)-15TI
50 0.3 AT28C256(E,F)-15DM/883
AT28C256(E,F)-15FM/883 AT28C256(E,F)-15LM/883 AT28C256(E,F)-15UM/883
AT28C256(E,F)-20PC AT28C256(E,F)-20SC AT28C256(E,F)-20TC
AT28C256(E,F)-20JI AT28C256(E,F)-20PI AT28C256(E,F)-20SI AT28C256(E,F)-20TI
50 0.3 AT28C256(E,F)-20DM/883
AT28C256(E,F)-20FM/883 AT28C256(E,F)-20LM/883 AT28C256(E,F)-20UM/883
32J 28P6 28S 28T
32J 28P6 28S 28T
28D6 28F 32L 28U
32J 28P6 28S 28T
32J 28P6 28S 28T
28D6 28F 32L 28U
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Package Type
28D6 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip)
28F 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack)
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32L 32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC)
28P6 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28T 28-lead, Plastic Thin Small Outline Package (TSOP)
28U 28-pin, Ceramic Pin Grid Array (PGA)
W Die
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
E High Endurance Option: Endurance = 100K Write Cycles
F Fast Write Option: Write Time = 3 ms
0006I–PEEPR–4/05
13
27.1 Standard Package (Continued)
I
t
ACC
(ns)
250 50 0.2 AT28C256(E,F)-25JC
(3)
150
(mA)
CC
Ordering Code Package Operation RangeActive Standby
AT28C256(E,F)-25PC AT28C256-W
AT28C256(E,F)-25JI AT28C256(E,F)-25PI
50 0.3 AT28C256(E,F)-25DM/883
AT28C256(E,F)-25FM/883 AT28C256(E,F)-25LM/883 AT28C256(E,F)-25UM/883 AT28C256(E,F)-35UM/883
50 0.3 5962-88525 16 UX
5962-88525 16 XX 5962-88525 16 YX 5962-88525 16 ZX
5962-88525 15 UX 5962-88525 15 XX 5962-88525 15 YX 5962-88525 15 ZX
5962-88525 14 UX 5962-88525 14 XX 5962-88525 14 YX 5962-88525 14 ZX
32J 28P6 DIE
32J 28P6
28D6 28F 32L 28U 28U
28U 28D6 32L 28F
28U 28D6 32L 28F
28U 28D6 32L 28F
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Package Type
28D6 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip)
28F 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack)
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32L 32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC)
28P6 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28U 28-pin, Ceramic Pin Grid Array (PGA)
W Die
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
E High Endurance Option: Endurance = 100K Write Cycles
F Fast Write Option: Write Time = 3 ms
14
AT28C256
0006I–PEEPR–4/05
27.1 Standard Package (Continued)
I
t
ACC
(ns)
150
200
250
(3)
(3)
(3)
(mA)
CC
Ordering Code Package Operation RangeActive Standby
50 0.3 5962-88525 08 UX
5962-88525 08 XX 5962-88525 08 YX 5962-88525 08 ZX
5962-88525 07 UX 5962-88525 07 XX 5962-88525 07 YX 5962-88525 07 ZX
5962-88525 06 UX 5962-88525 06 XX 5962-88525 06 YX 5962-88525 06 ZX
50 0.3 5962-88525 12 UX
5962-88525 12 XX 5962-88525 12 YX 5962-88525 12 ZX
50 0.3 5962-88525 04 UX
5962-88525 04 XX 5962-88525 04 YX 5962-88525 04 ZX
50 0.3 5962-88525 13 UX
5962-88525 13 XX 5962-88525 13 YX 5962-88525 13 ZX
5962-88525 11 UX 5962-88525 11 XX 5962-88525 11 YX 5962-88525 11 ZX
28U 28D6 32L 28F
28U 28D6 32L 28F
28U 28D6 32L 28F
28U 28D6 32L 28F
28U 28D6 32L 28F
28U 28D6 32L 28F
28U 28D6 32L 28F
AT28C256
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Package Type
28D6 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip)
28F 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack)
32L 32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC)
28U 28-pin, Ceramic Pin Grid Array (PGA)
W Die
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
E High Endurance Option: Endurance = 100K Write Cycles
F Fast Write Option: Write Time = 3 ms
0006I–PEEPR–4/05
15
27.1 Standard Package (Continued)
I
t
ACC
(ns)
250 50 0.3 5962-88525 05 UX
300 50 0.3 5962-88525 10 UX
350 50 0.3 5962-88525 09 UX
Notes: 1. Electrical specifications for these speeds are defined by Standard Microcircuit Drawing 5962-88525.
2. See “Valid Part Numbers” on page 18.
3. SMD specifies Software Data Protection feature for device type, although Atmel product supplied to every device type in the SMD is 100% tested for this feature.
(mA)
CC
Ordering Code Package Operation RangeActive Standby
5962-88525 05 XX 5962-88525 05 YX 5962-88525 05 ZX
5962-88525 03 UX 5962-88525 03 XX 5962-88525 03 YX 5962-88525 03 ZX
5962-88525 10 XX 5962-88525 10 YX 5962-88525 10 ZX
50 0.3 5962-88525 02 UX
5962-88525 02 XX 5962-88525 02 YX 5962-88525 02 ZX
5962-88525 09 XX 5962-88525 09 YX 5962-88525 09 ZX
50 0.3 5962-88525 01 UX
5962-88525 01 XX 5962-88525 01 YX 5962-88525 01 ZX
28U 28D6 32L 28F
28U 28D6 32L 28F
28U 28D6 32L 28F
28U 28D6 32L 28F
28U 28D6 32L 28F
28U 28D6 32L 28F
Class B, Fully Compliant
(-55°C to 125°C)
Class B, Fully Compliant
(-55°C to 125°C)
Class B, Fully Compliant
(-55°C to 125°C)
Class B, Fully Compliant
(-55°C to 125°C)
Class B, Fully Compliant
(-55°C to 125°C)
Class B, Fully Compliant
(-55°C to 125°C)
Military/883C
Military/883C
Military/883C
Military/883C
Military/883C
Military/883C
Package Type
28D6 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip)
28F 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack)
32L 32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC)
28U 28-pin, Ceramic Pin Grid Array (PGA)
W Die
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
E High Endurance Option: Endurance = 100K Write Cycles
F Fast Write Option: Write Time = 3 ms
16
AT28C256
0006I–PEEPR–4/05

27.2 Green Package Option (Pb/Halide-free)

I
t
ACC
(ns)
150 50 0.2 AT28C256(F)-15JU
CC
(mA)
Ordering Code Package Operation RangeActive Standby
AT28C256(F)-15PU AT28C256(F)-15SU AT28C256(F)-15TU
32J 28P6 28S 28T
AT28C256
Industrial
(-40°C to 85°C)
Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28T 28-lead, Plastic Thin Small Outline Package (TSOP)
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
F Fast Write Option: Write Time = 3 ms
0006I–PEEPR–4/05
17

28. Valid Part Numbers

The following table lists standard and green Atmel products that can be ordered.
Device Numbers Speed Package and Temperature Combinations
AT28C256 15 JC, JI, JU, PC, PI, PU, SC, SI, SU, TC, TI, TU, DM/883, FM/883, LM/883, UM/883
AT28C256E 15 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256F 15 JC, JI, JU, PC, PI, PU, SC, SI, SU, TC, TI, TU, DM/883, FM/883, LM/883, UM/883
AT28C256 20 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256E 20 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256F 20 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256 25 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256E 25 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256F 25 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883
AT28C256 –W

29. Die Products

Reference Section: Parallel EEPROM Die Products
18
AT28C256
0006I–PEEPR–4/05
Packaging Information
29.1 28D6 – Cerdip
Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 D-10 Config A (Glass Sealed)
37.85(1.490)
36.58(1.440)
AT28C256
PIN
1
15.49(0.610)
12.95(0.510)
5.72(0.225)
SEATING
PLANE
5.08(0.200)
3.18(0.125)
2325 Orchard Parkway
R
San Jose, CA 95131
33.02(1.300) REF
MAX
1.65(0.065)
2.54(0.100)BSC
1.14(0.045)
15.70(0.620)
15.00(0.590)
0.46(0.018)
0.20(0.008)
TITLE
28D6, 28-lead, 0.600" Wide, Non-windowed,
Ceramic Dual Inline Package (Cerdip)
0.127(0.005)MIN
1.52(0.060)
0.38(0.015)
0.66(0.026)
0.36(0.014)
0º~ 15º REF
17.80(0.700) MAX
DRAWING NO.
28D6
10/23/03
REV.
B
0006I–PEEPR–4/05
19
29.2 28F – Flatpack
PIN #1 ID
9.40(0.370)
6.35(0.250)
0.56(0.022)
0.38(0.015)
1.27(0.050) BSC
1.14(0.045) MAX
3.02(0.119)
2.29(0.090)
1.14(0.045)
0.660(0.026)
7.26(0.286)
6.96(0.274)
1.96(0.077)
1.09(0.043)
0.23(0.009)
0.10(0.004)
10.57(0.416)
9.75(0.384)
Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 F-12 Config B
20
2325 Orchard Parkway
R
San Jose, CA 95131
AT28C256
TITLE
28F, 28-lead, Non-windowed, Ceramic Bottom-brazed
Flat Package (FlatPack)
DRAWING NO.
28F
0006I–PEEPR–4/05
10/21/03
REV.
B
29.3 32J – PLCC
AT28C256
1.14(0.045) X 45˚
B
e
0.51(0.020)MAX
45˚ MAX (3X)
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
PIN NO. 1 IDENTIFIER
D1
D
D2
1.14(0.045) X 45˚
E1 E
0.318(0.0125)
0.191(0.0075)
E2
B1
A2
A1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A 3.175 3.556
A1 1.524 2.413
A2 0.381
D 12.319 12.573
D1 11.354 11.506 Note 2
D2 9.906 10.922
E 14.859 15.113
E1 13.894 14.046 Note 2
E2 12.471 13.487
B 0.660 0.813
B1 0.330 0.533
e 1.270 TYP
MIN
NOM
MAX
NOTE
10/04/01
2325 Orchard Parkway
R
San Jose, CA 95131
0006I–PEEPR–4/05
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
32J
REV.
B
21
29.4 32L – LCC
Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 C-12
11.63(0.458)
11.23(0.442)
2.54(0.100)
2.16(0.085)
14.22(0.560)
13.72(0.540)
10.16(0.400) BSC
2325 Orchard Parkway
R
San Jose, CA 95131
1.91(0.075)
1.40(0.055)
INDEX CORNER
X 45˚
RADIUS
2.41(0.095)
1.91(0.075)
1.27(0.050) TYP
PIN 1
1.40(0.055)
1.14(0.045)
7.62(0.300) BSC
0.635(0.025)
0.381(0.015)
0.305(0.012)
0.178(0.007)
0.737(0.029)
0.533(0.021)
1.02(0.040) X 45˚
2.16(0.085)
1.65(0.065)
TITLE
32L, 32-pad, Non-windowed, Ceramic Lid, Leadless Chip
Carrier (LCC)
DRAWING NO.
32L
10/21/03
REV.
B
22
AT28C256
0006I–PEEPR–4/05
29.5 28P6 – PDIP
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
AT28C256
D
e
0º ~ 15º
eB
Notes: 1. This package conforms to JEDEC reference MS-011, Variation AB.
2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
TITLE
2325 Orchard Parkway
R
San Jose, CA 95131
28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A 4.826
A1 0.381
D 36.703 37.338 Note 2
E 15.240 15.875
E1 13.462 13.970 Note 2
B 0.356 0.559
B1 1.041 1.651
L 3.048 3.556
C 0.203 0.381
eB 15.494 17.526
e 2.540 TYP
MIN
NOM
MAX
DRAWING NO.
28P6
NOTE
09/28/01
REV.
B
0006I–PEEPR–4/05
23
29.6 28S – SOIC
Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters.
0.51(0.020)
0.33(0.013)
PIN 1
TOP VIEW
18.10(0.7125)
17.70(0.6969)
0.30(0.0118)
0.10(0.0040)
0º ~ 8º
7.60(0.2992)
7.40(0.2914)
1.27(0.50) BSC
1.27(0.050)
0.40(0.016)
10.65(0.419)
10.00(0.394)
2.65(0.1043)
2.35(0.0926)
SIDE VIEWS
0.32(0.0125)
0.23(0.0091)
24
2325 Orchard Parkway
R
San Jose, CA 95131
AT28C256
TITLE
28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC)
JEDEC Standard MS-013
DRAWING NO.
28S
0006I–PEEPR–4/05
8/4/03
REV.
B
29.7 28T – TSOP
AT28C256
PIN 1
Pin 1 Identifier Area
D1
D
e
E
b
A2
A
A1
Notes: 1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
0º ~ 5º
SEATING PLANE
SYMBOL
c
L
L1
GAGE PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
A 1.20
A1 0.05 0.15
A2 0.90 1.00 1.05
D 13.20 13.40 13.60
D1 11.70 11.80 11.90 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 0.21
e 0.55 BASIC
NOM
MAX
NOTE
2325 Orchard Parkway
R
San Jose, CA 95131
0006I–PEEPR–4/05
TITLE
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
28T
12/06/02
REV.
C
25
29.8 28U – PGA
Dimensions in Millimeters and (Inches). Controlling dimension: Inches.
7.26(0.286)
6.50(0.256)
16.71(0.658)
16.31(0.642)
13.74(0.540)
13.36(0.526)
14.17(0.558)
13.77(0.542)
2.57(0.101)
2.06(0.081)
15.24(0.600)
14.88(0.586)
2.54(0.100) TYP
12.70(0.500) TYP
1.40(0.055)
1.14(0.045)
0.58(0.023)
0.43(0.017)
3.12(0.123)
2.62(0.103)
1.83(0.072)
1.57(0.062)
26
2325 Orchard Parkway
R
San Jose, CA 95131
AT28C256
2.54(0.100) TYP
10.41(0.410)
9.91(0.390)
TITLE
28U, 28-pin, Ceramic Pin Grid Array (PGA)
DRAWING NO.
28U
0006I–PEEPR–4/05
10/21/03
REV.
B
Atmel Corporation Atmel Operations
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN­TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
© Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, and others, are registered trademarks, and Everywhere You Are trademarks of others.
SM
and others are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be
Printed on recycled paper.
0006I–PEEPR–4/05
Loading...