ATMEL AT28C256 User Manual

Features

• Fast Read Access Time – 150 ns

• Automatic Page Write Operation

– Internal Address and Data Latches for 64 Bytes – Internal Control Timer

• Fast Write Cycle Times

– Page Write Cycle Time: 3 ms or 10 ms Maximum – 1 to 64-byte Page Write Operation

• Low Power Dissipation

– 50 mA Active Current –200 µA CMOS Standby Current

• Hardware and Software Data Protection

• DATA Polling for End of Write Detection

• High Reliability CMOS Technology

– Endurance: 104 or 105 Cycles – Data Retention: 10 Years

• Single 5V ± 10% Supply

• CMOS and TTL Compatible Inputs and Outputs

• JEDEC Approved Byte-wide Pinout

• Full Military, Commercial, and Industrial Temperature Ranges

• Green (Pb/Halide-free) Packaging Option

256K (32K x 8) Paged Parallel EEPROM

AT28C256

1. Description

The AT28C256 is a high-performance electrically erasable and programmable readonly memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 200 µA.

The AT28C256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA new access for a read or write can begin.

Atmel’s AT28C256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking.

Polling of I/O7. Once the end of a write cycle has been detected a

0006I–PEEPR–4/05

2. Pin Configurations

Pin Name Function

A0 - A14 Addresses

Chip Enable

Output Enable

Write Enable

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

DC Don’t Connect

2.1 28-lead TSOP Top View

A11

A9 A8

A13

VCC

A14 A12

A7 A6 A5 A4 A3

2 3 4 5 6 7 8 9 10 11 12 13 14

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

2.3 32-pad LCC, 28-lead PLCC Top View

A12

A14DCVCCWEA13

A6 A5 A4 A3 A2 A1 A0

I/O0

432

5 6 7 8 9 10 11 12 13

14151617181920

I/O1

I/O2

GND

323130

I/O3

I/O4

29 28 27 26 25 24 23 22 21

I/O5

A8 A9 A11 NC OE A10 CE I/O7 I/O6

2.2 28-lead PGA Top View

AT28C256

Note: PLCC package pins 1 and 17 are Don’t Connect.

2.4 28-lead Cerdip/PDIP/Flatpack/SOIC – Top View

A14 A12

A7 A6 A5 A4 A3 A2 A1

A0 I/O0 I/O1 I/O2

GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14

VCC

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

0006I–PEEPR–4/05

3. Block Diagram

4. Device Operation

4.1 Read

The AT28C256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE control gives designers flexibility in preventing bus contention in their system.

AT28C256

or OE is high. This dual-line

4.2 Byte Write

4.3 Page Write

4.4 DATA Polling

A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE latched by the first rising edge of CE cally time itself to completion. Once a programming operation has been initiated and for the duration of t

The page write operation of the AT28C256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs (t limit is exceeded the AT28C256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. For each WE write operation, A6 - A14 must be the same.

The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.

The AT28C256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA cycle.

, a read operation will effectively be a polling operation.

or WE. Once a byte write has been started it will automati-

or WE, whichever occurs last. The data is

) of the previous byte. If the t

BLC

high to low transition during the page

Polling may begin at anytime during the write

BLC

0006I–PEEPR–4/05

4.5 Toggle Bit

In addition to DATA Polling the AT28C256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.

4.6 Data Protection

If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes.

4.6.1 Hardware Protection

Hardware features protect against inadvertent writes to the AT28C256 in the following ways: (a) V

sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay –

once V a write; (c) write inhibit – holding any one of OE and (d) noise filter – pulses of less than 15 ns (typical) on the WE write cycle.

4.6.2 Software Data Protection

A software controlled data protection feature has been implemented on the AT28C256. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C256 is shipped from Atmel with SDP disabled.

has reached 3.8V the device will automatically time out 5 ms (typical) before allowing

low, CE high or WE high inhibits write cycles;

or CE inputs will not initiate a

SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to “Software Data Protection” algorithm). After writing the 3-byte command sequence and after t protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28C256. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP.

Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28C256 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation.

After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of

, read operations will effectively be polling operations.

4.7 Device Identification

An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array.

the entire AT28C256 will be

4.8 Optional Chip Erase Mode

The entire device can be erased using a 6-byte software code. Please see “Software Chip Erase” application note for details.

AT28C256

0006I–PEEPR–4/05

AT28C256

5. DC and AC Operating Range

AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35

Operating Temperature (Case)

Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

6. Operating Modes

Mode CE OE WE I/O

Read V

(2)

Write

Standby/Write Inhibit V

Write Inhibit X X V

Write Inhibit X V

Output Disable X V

Chip Erase V

Notes: 1. X can be VIL or VIH.

2. Refer to AC programming waveforms.

= 12.0V ± 0.5V.

3. V

Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C

Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C

Mil. -55°C - 125°C -55°C - 125°C -55°C - 125°C -55°C - 125°C

(1)

(3)

X High Z

High Z

OUT

7. Absolute Maximum Ratings*

Temperature under Bias ................................ -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

and A9

+ 0.6V

with Respect to Ground...................................-0.6V to +13.5V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

8. DC Characteristics

Symbol Parameter Condition Min Max Units

SB1

SB2

Input Load Current VIN = 0V to VCC + 1V 10 µA

Output Leakage Current V

VCC Standby Current CMOS CE = V

= 0V to V

I/O

- 0.3V to VCC + 1V

10 µA

Com., Ind. 200 µA

Mil. 300 µA

VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA

Active Current f = 5 MHz; I

= 0 mA 50 mA

OUT

Input Low Voltage 0.8 V

Input High Voltage 2.0 V

Output Low Voltage IOL = 2.1 mA 0.45 V

Output High Voltage IOH = -400 µA 2.4 V

0006I–PEEPR–4/05

9. AC Read Characteristics

Symbol Parameter

AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35

UnitsMin Max Min Max Min Max Min Max

ACC

(1)

(2)

(3)(4)

Address to Output Delay 150 200 250 350 ns

CE to Output Delay 150 200 250 350 ns

OE to Output Delay 0 70 0 80 0 100 0 100 ns

CE or OE to Output Float 050055060070 ns

Output Hold from OE, CE or

Address, whichever occurred first

10. AC Read Waveforms

0000 ns

(1)(2)(3)(4)

Notes: 1. CE may be delayed up to t

2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by t without impact on t

is specified from OE or CE whichever occurs first (CL = 5 pF).

3. t

ACC

4. This parameter is characterized and is not 100% tested.

- tCE after the address transition without impact on t

ACC

- tOE after an address change

ACC

AT28C256

0006I–PEEPR–4/05

11. Input Test Waveforms and Measurement Level

tR, tF < 5 ns

12. Output Test Load

13. Pin Capacitance

f = 1 MHz, T = 25°C

(1)

AT28C256

Symbol Typ Max Units Conditions

OUT

Note: 1. This parameter is characterized and is not 100% tested.

46pFV

812pFV

OUT

= 0V

0006I–PEEPR–4/05

14. AC Write Characteristics

Symbol Parameter Min Max Units

tAS, t

OES

tDH, t

OEH

Note: 1. NR = No Restriction

Address, OE Setup Time 0 ns

Address Hold Time 50 ns

Chip Select Setup Time 0 ns

Chip Select Hold Time 0 ns

Write Pulse Width (WE or CE) 100 ns

Data Setup Time 50 ns

Data, OE Hold Time 0 ns

Time to Data Valid NR

(1)

15. AC Write Waveforms

15.1 WE Controlled

15.2 CE

AT28C256

Controlled

0006I–PEEPR–4/05

AT28C256

16. Page Mode Characteristics

Symbol Parameter Min Max Units

Write Cycle Time (option available)

AT28C256 10 ms

AT28C256F 3 ms

BLC

WPH

Address Setup Time 0 ns

Address Hold Time 50 ns

Data Setup Time 50 ns

Data Hold Time 0 ns

Write Pulse Width 100 ns

Byte Load Cycle Time 150 µs

Write Pulse Width High 50 ns

17. Page Mode Write Waveforms

(1)(2)

Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE).

must be high only when WE and CE are both low.

2. OE

18. Chip Erase Waveforms

tS = tH = 5 µsec (min.)

= 10 msec (min.)

= 12.0V ± 0.5V

0006I–PEEPR–4/05

+ 18 hidden pages