ATMEL AT28C17E-15PI, AT28C17E-15PC, AT28C17E-15JI, AT28C17E-15JC, AT28C17-W Datasheet
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AT28C17
16K (2K x 8)
CMOS
E2PROM
Features
0541A
Fast Read Access Time - 150 ns
•
Fast Byte Write - 200 µs or 1 ms
•
Self-Timed Byte Write Cycle
•
Internal Address and Data Latches
Internal Control Timer
Automatic Clear Before Write
Direct Microprocessor Con trol
•
DATA POLLING
READY/BUSY Open Drain Output
Low Power
•
30 mA Active Current
100 µa CMOS Standby Current
High Reliabili ty
•
Endurance: 104 or 105 Cycles
Data Retention: 10 Years
5V ± 10% Supply
•
CMOS & TTL Compatible Inpu ts an d Outp uts
•
JEDEC Approved Byte Wide Pino ut
•
Commercial and Industrial Temperature Ranges
•
Description
The AT28C17 is a low-power, high-performance Electrically Erasable and Programmable Read Only Memory with easy to use features. The AT28C17 is a 16K memory
organized as 2,048 words by 8 bits. The device is manufac tured with Atmel’s reliable
nonvolatile CMOS technology.
(continued)
Pin Configurations
AT28C17
Pin Name Function
A0 - A10 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
RDY/
BUSY Ready/Busy Output
NC No Connect
DC Don’t Connec t
PDIP, SOIC
PLCC
Top View
Top View
Note: PLCC package pins 1 and
17 are DON’T CONNECT.
2-183
Description (Continued)
The AT28C17 is accessed like a static RAM for the read
or write cycles without the need of external components.
During a byte write, the address and data are latched internally, freeing the microprocessor addr ess and data bus
for other operations. Following the initiation of a write cycle, the device will go to a busy state and automatically
clear and write the latched data using an internal control
timer. The device includes two methods for detecting the
end of a write cycle, level detection of RDY/
DATA POLLING of I/O7. Once the end of a write cycle has
been detected, a new access for a read or a write can
begin.
BUSY and
Block Diagram
The CMOS technology offers fast access times of 150 ns
at low power dissipation. When the chip is deselected the
standby current is less than 100 µA.
Atmel’s 28C17 has additional features to ensure high
quality and manufacturability. The device utilizes error correction int ernally for extended e ndurance and for improved data retention characteristics. An extra 32-bytes of
2
PROM are available for device identification or tracking.
E
Absolute Maximum Ratings*
Temperature Under Bias.................-55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
2-184 AT28C17
+ 0.6V
CC
*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-
mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Device Operation
READ: The AT28C17 is accessed like a Static RAM.
CE and OE are low and WE is high, the data stored
When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in a high impedance state whenever
control gives designers increased flexibility in preventing
bus contention.
BYTE WRITE: Writing data into the AT28C17 is similar to
writing into a Static RAM. A low pulse on the
input with
ates a byte write. The address location is latched on the
last falling edge of
the first rising edge. Internally, the device performs a selfclear before write. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated and for the duration of t
operation.
FAST BYTE WRITE: The AT28C17E offers a byte write
time of 200 µs maximum. This feature allows the entire
device to be rewritten in 0.4 seconds.
READY/
output that can be used to detect the end of a write cycle.
RDY/
and is released at the completion of the write. The open
drain connection allows for OR-tying of several devices to
the same RDY/
OE high and CE or WE low (respectively) initi-
WE (or CE); the new data is latched on
, a read operation will effectively be a polling
WC
BUSY: Pin 1 is an open drain READY/BUSY
BUSY is actively pulled low during the write cycle
BUSY line.
CE or OE is high. This dual line
WE or CE
AT28C17
DATA POLLING: The AT28C17 provides DA TA POLL-
ING to signal t he completion of a write cycle. During a
write cycle, an attempted read of the data being written
results in the complement of that data for I/O
outputs are indeterminate). When the write cycle is finished, true data appears on all outputs.
WRITE PROTECTION: Inadvertent writes to the device
are protec ted against in the following ways. (a) V
sense— if VCC is below 3.8V (typical) the write function is
inhibited. (b) V
reached 3.8V the device will automatically time out 5 ms
(typical) before allowing a byte write. (c) Write Inhibit—
holding any one of
byte write cycles.
CHIP CLEAR: The contents of the entire memory of the
AT28C17 may be set to the high state by the CHIP CLEAR
operation. By setting
is cleared when a 10 msec low pulse is applied to
DEVICE IDENTIFICATION: A n extra 32-byt es of
2
PROM memory are available to the user for device
E
identification. By raising A9 to 12 ± 0.5V and using address locations 7E0H to 7FFH the additional bytes may be
written to or read from in the same manner as the regular
memory array.
power on delay— once VCC has
CC
OE low, CE high or WE high inhibits
CE low and OE to 12 volts, the chip
(the other
7
WE.
CC
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