ATMEL AT28C010E-25UM-883, AT28C010E-25LM-883, AT28C010E-25EM-883, AT28C010E-25DM-883, AT28C010E-20UM-883 Datasheet

AT28C010 Mil

1 Megabit
(128K x 8)
Paged
CMOS
E2PROM

Military

Features

0353C

Fast Read Access Time - 120 ns

•

Automatic Page Write Operation

•

Internal Address and Data Latches for 128-Bytes
Internal Control Timer

Fast Write Cycle Tim e

•

Page Write Cycle Time - 10 ms Maximum
1 to 128-Byte Page Write Ope rati on

Low Power Dissipation

•

80 mA Active Current
300 µA CMOS Standby Current

Hardware and Software Data Protection

•

DATA Polling for End of Write Dete cti on

•

High Reliabili ty C MOS Technology

•

Endurance: 104 or 105 Cycles
Data Retention: 10 Years

Single 5V ± 10% Supply

•

CMOS and TTL Compatible Inputs and Outputs

•

JEDEC Approved Byte-Wid e Pin ou t

•

Description

The AT28C010 is a high-performance Electrically Erasable and Progr ammable Read
Only Memory. Its one megabit of memory is organized as 131,072 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology , the device offers

(continued)

Pin Configurations

44 LCC

Pin Name Function

A0 - A16 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect

Top View

AT28C010 Mil

PGA

Top View

CERDIP, FLATPACK

Top View

32 LCC

Top View

2-243

Description (Continued)

access times to 120 ns with power dissipation of just 440
mW. When the device is deselected, the CMOS standby
current is less than 300 µA.

The AT28C010 is accessed like a Static RAM for the read
or write cycle without the need for external components.
The device contains a 128-byte page register to allow writ­ing of up to 128-bytes simultaneously. During a write cy­cle, the address and 1 to 128-bytes of data are internally
latched, freeing the address and data bus for other opera­tions. Following the initiation of a write cycle, the device
will automatically write the latched data using an internal

Block Diagram

control timer. The end of a write cycle can be detected by
DATA POLLING of I/O7. Once the end of a write cycle has
been detected a new access for a read or write can begin.

Atmel’s 28C010 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correc tion for extended endurance and improved
data retention characteristics. An optional software data
protection mechanism is available to guard against inad­vertent w rites. The device also includes an extra 128­bytes of E

2

PROM for device identification or tracking.

Absolute Maximum Ratings*

Temperature Under Bias.................-55°C to +125°C

Storage Temperature...................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground .............-0.6V to V

Voltage on OE and A9

with Respect to Ground ................... -0.6V to +13.5V

2-244 AT28C010 Mil

+ 0.6V

CC

*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-

mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi­cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

Device Operation

READ: The AT28C010 is accessed like a Static RAM.

CE and OE are low and WE is high, the data stored

When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either
line control gives designers flexibility in preventing bus
contention in their system.

BYTE WRITE: A low pulse on the

WE low (respectively) and OE high initiates a write cy-

or
cle. The address is latched on the falling edge of
WE, whichever occurs last. The data is latched by the firs t
rising edge of
started it will automatically time itself to completion. Once
a programming operation has been initiated and for the
duration of t
ing operation.

PAGE WRITE: The page write operation of the AT28C010
allows 1 to 128-bytes of data to be written into the device
during a single internal programming period. A page write
operation is initiated in the same manner as a byte write;
the first byte written can then be followed by 1 to 127 ad­ditional bytes. Each successive byte must be written within
150 µs (t
ceeded the AT28C010 will cease accepting data and com­mence the internal programming operation. All bytes dur­ing a page write operation must reside on the same page
as defined by the state of the A7 - A16 inputs. For each
WE high to low transition during the page write operation,
A7 - A16 must be the same.

The A0 to A6 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.

DATA POLLING: The AT28C010 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complem ent of the written data to be pre­sented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin.
write cycle.

TOGGLE BIT: In addition to
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling be­tween one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.

CE or WE. Once a byte write has been

, a read operation will effectively be a poll-

WC

) of the previous byte. If the t

BLC

DATA Polling may begin at anytime during the

CE or OE is high. This dual-

WE or CE input with CE

CE or

limit is ex-

BLC

DATA Polling the AT28C010

AT28C010 Mil

DATA PROTECTION: If precautions are not taken, inad-

vertent writes may occur during transitions of the host sys­tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory agains t
inadvertent writes.

HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28C010 in the follow­ing ways: (a) V
write function is inhibited; (b) V

has reached 3.8V the device will automatically time

V

CC

out 5 ms (typical) before allowing a write: (c) write inhibit ­holding any one of
write cycles; (d) noise filter - pulses of less than 15 ns (typi­cal) on the

SOFTWARE DATA PROTECTION: A software controlled
data protection feature has been implemented on the
AT28C010. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C010 is
shipped from Atmel with SDP disabled.

SDP is enabled by the h ost system issuing a series of
three write co mmands; three specific bytes of data are
written to three specific addresses (refer to Software Data
Protection Algorithm). After writing the 3-byte command
sequence and after t
tected against inadvertent write operations. It should be
noted, that o nce protected the host may sti ll perform a
byte or page write to the AT28C010. This is done by pre­ceding the data to be written by the same 3-byte command
sequence used to enable SDP.

Once set, SDP will remain active unless the disable com­mand sequence is issued. Power transitions do not dis­able SDP and SDP will protect the AT28C010 during
power-up and power-down conditions. All command se­quences must conform to the page write timing specifica­tions. The data in the enable and disable command se­quences is not written to the device and the memory ad­dresses used in the sequence may be written with data in
either a byte or page write operation.

After setting SDP, any attempt to write to the device with­out the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of t
polling operations.

sense - if VCC is below 3.8V (typical) the

CC

power-on delay - once

CC

OE low, CE high or WE high inhibits

WE or CE inputs will not initiate a write cycle.

the entire AT28C010 will be pro-

WC

, read operations will effectively be

WC

(continued)

2-245

Device Operation (Continued)

DEVICE IDENTIFICATION: An extra 128-bytes of

2

PROM memory are available to the user for device

E
identification. By raising A9 to 12V ± 0.5V and using ad­dress locations 1FF80H to 1FFFFH the bytes may be writ­ten to or read from in the same manner as the regular
memory array.

OPTIONAL CHIP ERASE MODE: The entire device can
be erased using a 6-byte software code. Please see Soft­ware Chip Erase application note for details.

DC and AC Operating Range

AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25

Operating
Temperature (Case)

V

Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

CC

Mil. -55°C - 125°C -55°C - 125°C -55°C - 125°C -55°C - 125°C

Operating Modes

Mode CE OE WE I/O

Read V

(2)

Write
Standby/Write Inhibit V

IL

V

IL
IH

Write Inhibit X X V
Write Inhibit X V
Output Disable X V

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.

X

V

IL

V

IH
(1)

IL
IH

V

IH

V

IL

X High Z

IH

X
X High Z

D
D

OUT
IN

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

CC

V

IL

V

IH

V

OL

V

OH1

V

OH2

2-246 AT28C010 Mil

Input Load Current VIN = 0V to VCC + 1V 10 µA
Output Leakage Current V
VCC Standby Current CMOS CE = V

= 0V to V

I/O

CC

CC

10 µA

- 0.3V to VCC + 1V 300 µA
VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 m A
V

Active Current f = 5 MHz; I

CC

= 0 mA 80 mA

OUT

Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA .45 V
Output High Voltage IOH = -400 µA 2.4 V
Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

AC Read Characteristics

Symbol Parameter

t

ACC

(1)

t

CE

(2)

t

OE

(3, 4)

t

DF

t

OH

Address to Output Delay 120 150 200 250 ns
CE to Output Delay 120 150 200 250 ns
OE to Output Delay 0 50 0 55 0 55 0 55 ns
CE or OE to Output

Float
Output Hold from OE,

CE or Address,
whichever occurred first

AT28C010 Mil

AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25

Min Max Min Max Min Max Min Max

050055055055ns

0000ns

Units

AC Read Waveforms

Notes: 1. CE may be delayed up to t

transition without impact on t
OE may be delayed up to tCE - tOE after the falling

2.
edge of
after an address change without impact on t

CE without impact on tCE or by t

(1, 2, 3, 4)

- tCE after the address

ACC

ACC

Input Test Waveforms and
Measurement Level

3. tDF is specified from OE or CE whichever occu r s first

.

- tOE

ACC

.

ACC

(C

= 5 pF).

L

4. This parameter is characterized and is not 100% tested.

Output Test Load

tR, tF < 5 ns

Pin Capacitance (f = 1 MHz, T = 25° C)

(1)

Typ Max Units Conditions

C

IN

C

OUT

Note: 1. This parameter is characterized and is not 100% tested.

410pFV
812pFV

= 0V

IN

= 0V

OUT

2-247

AC Write Characteristics

Symbol Parameter Min Max Units

t
t
t
t
t
t
t

AS
AH
CS
CH
WP
DS
DH

, t

, t

OES

OEH

Address, OE Set-up Time 0 ns
Address Hold Time 50 ns
Chip Select Set-up Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE) 100 ns
Data Set-up Time 50 ns
Data, OE Hold Time 0 ns

AC Write Waveforms

WE Controlled

CE Controlled

2-248 AT28C010 Mil

AT28C010 Mil

Page Mode Characteristic s

Symbol Parameter Min Max Units

t

WC

t

AS

t

AH

t

DS

t

DH

t

WP

t

BLC

t

WPH

Write Cycle Time 10 ms
Address Set-up Time 0 ns
Address Hold Time 50 ns
Data Set-up Time 50 ns
Data Hold Time 0 ns
Write Pulse Width 100 ns
Byte Load Cycle Time 150 µs
Write Pulse Width High 50 ns

Page Mode Write Waveform s

(1, 2)

Notes: 1. A7 through A16 must specify the page address during each high to low transition of WE (or CE).

2.

OE must be high only when WE and CE are both low.

Chip Erase Waveforms

tS = 5 µsec (min. )

= tH = 10 msec (min.)

t

W

VH = 12.0V ± 0.5V

2-249

Software Data
Protection Enable

Algorithm

(1)

Software Data
Protection Dis abl e

Algorithm

(1)

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA A0

TO

ADDRESS 5555

LOAD DATA XX

TO

ANY ADDRESS

LOAD LAST BYTE

TO

LAST ADDRESS

WRITES ENABLED

(4)

ENTER DATA
PROTECT STATE

(2)

Notes:

1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).

2. Write Protect stat e wil l be act iv ated at end of write eve n if no
other data is loaded.

3. Write Protect stat e wil l be dea ctivated at end of write period
even if no oth er data is loaded .

4. 1 to 128-bytes of da ta are loaded.

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA 80

TO

ADDRESS 5555

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA 20

TO

ADDRESS 5555

LOAD DATA XX

TO

ANY ADDRESS

LOAD LAST BYTE

TO

LAST ADDRESS

EXIT DATA
PROTECT STATE

(4)

(3)

Software Protected Progr am Cyc le Wave for m

Notes: 1. A0 - A14 must conform to the addressing sequence for

the first 3-bytes as shown above.

2. After the command sequence has been issued and a
page write operation follows, the pag e address inputs
(A7 - A16) must be the same for each high to low
transition of

WE (or CE).

3. OE must be high only when WE and CE are both low.

(1, 2, 3)

2-250 AT28C010 Mil

AT28C010 Mil

Data Polling Characteristics

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

WR

Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics.

Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
Write Recovery Time 0 ns

(1)

(2)

Data Polling Waveforms

ns

Toggle Bit Characteristics

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

OEHP

t

WR

Notes: 1. These parameters are characterized and not 100% tested.

Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
OE High Pulse 150 ns
Write Recovery Time 0 ns

Toggle Bit Waveforms

(1)

(2)

2. See AC Read Characteristics.

(1, 2, 3)

ns

Notes: 1. Toggling either OE or CE or both OE and CE will

operate toggle bit.

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address
should not vary.

2-251

Ordering Information

(1)

t

ACC

(ns)

120 80 0.3 AT28C010(E)-12DM/883 32D6 Military/883C

150 80 0.3 AT28C010(E)-15DM/883 32D6 Military/883C

200 80 0.3 AT28C010(E)-20DM/883 32D6 Military/883C

250 80 0.3 AT28C010(E)-25DM/883 32D6 Military/883C

120 80 0.3 5962-38267 07 MXX 32D6 Military/883C

150 80 0.3 5962-38267 05 MXX 32D6 Military/883C

200 80 0.3 5962-38267 03 MXX 32D6 Military/883C

250 80 0.3 5962-38267 01 MXX 32D6 Military/883C

ICC (mA)

Ordering Code

Active Standby

AT28C010(E)-12EM/883 32L Class B, Fully Compliant
AT28C010-12FM/883 32F (-55°C to 125°C)
AT28C010(E)-12LM/883 44L
AT28C010(E)-12UM/883 30U

AT28C010(E)-15EM/883 32L Class B, Fully Compliant
AT28C010-15FM/883 32F (-55°C to 125°C)
AT28C010(E)-15LM/883 44L
AT28C010(E)-15UM/883 30U

AT28C010(E)-20EM/883 32L Class B, Fully Compliant
AT28C010-20FM/883 32F (-55°C to 125°C)
AT28C010(E)-20LM/883 44L
AT28C010(E)-20UM/883 30U

AT28C010(E)-25EM/883 32L Class B, Fully Compliant
AT28C010-25FM/883 32F (-55°C to 125°C)
AT28C010(E)-25LM/883 44L
AT28C010(E)-25UM/883 30U

5962-38267 07 MZX 32F Class B, Fully Compliant
5962-38267 07 MYX 44L (-55°C to 125°C)
5962-38267 07 MTX 30U

5962-38267 05 MUX 32L Class B, Fully Compliant
5962-38267 05 MZX 32F (-55°C to 125°C)
5962-38267 05 MYX 44L
5962-38267 05 MTX 30U

5962-38267 03 MUX 32L Class B, Fully Compliant
5962-38267 03 MZX 32F (-55°C to 125°C)
5962-38267 03 MYX 44L
5962-38267 03 MTX 30U

5962-38267 01 MUX 32L Class B, Fully Compliant
5962-38267 01 MZX 32F (-55°C to 125°C)
5962-38267 01 MYX 44L
5962-38267 01 MTX 30U

80 0.3 AT28C010-W DIE

Package Operation Range

Note: 1. See Valid Part Number table on next page.

2-252 AT28C010 Mil

Valid Part Numbers

The following table lists standard Atmel products that can be ordered.

Device Numbers Speed Package and Temperature Combinations

AT28C010 Mil

AT28C010
AT28C010E
AT28C010
AT28C010E
AT28C010
AT28C010E
AT28C010
AT28C010E

12
12
15
15
20
20
25
25

DM/883, EM/883, FM/883, LM/883, UM/883
DM/883, EM/883, LM/883, UM/883
DM/883, EM/883, FM/883, LM/883, UM/883
DM/883, EM/883, LM/883, UM/883
DM/883, EM/883, FM/883, LM/883, UM/883
DM/883, EM/883, LM/883, UM/883
DM/883, EM/883, FM/883, LM/883, UM/883
DM/883, EM/883, LM/883, UM/883

Package Type

32D6 32 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inlin e (CERDIP)
32F 32 Lea d, Non-Windowed, Ceramic Bot to m-Bra ze d Fl at Pa ckag e (Fl atpack)
32L 32 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
44L 44 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
30U 30 Pin, Ceramic Pin Grid Array (PGA)
W Die

Options

Blank Standard Device : End urance = 10K Write Cycles; Write Time = 10 ms
E High Endurance Option: Endurance = 100K Write Cycles

2-253