ATMEL AT28C010E-20TI, AT28C010E-15TC, AT28C010E-15PI, AT28C010E-15PC, AT28C010E-15JI Datasheet
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AT28C010 Com/Ind
1 Megabit
(128K x 8)
Paged
CMOS
E2PROM
Commercial
and
Industrial
Features
0353C
Fast Read Access Time - 120 ns
•
Automatic Page Write Operation
•
Internal Address and Data Latches for 128-Bytes
Internal Control Timer
Fast Write Cycle Tim e
•
Page Write Cycle Time - 10 ms Maximum
1 to 128-Byte Page Write Ope rati on
Low Power Dissipation
•
40 mA Active Current
200 µA CMOS Standby Current
Hardware and Software Data Protection
•
DATA Polling for End of Write Dete cti on
•
High Reliabili ty C MOS Technology
•
Endurance: 104 or 105 Cycles
Data Retention: 10 Years
Single 5V ± 10% Supply
•
CMOS and TTL Compatible Inputs and Outputs
•
JEDEC Approved Byte-Wid e Pin ou t
•
Commercial and Industrial Temperature Ranges
•
Description
The AT28C010 is a high-performance Electrically Erasable and Progr ammable Read
Only Memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology , the device offers
access times to 120 ns with power dissipation of just 220 mW. W hen the device is
deselected, the CMOS standby current is less than 200 µA.
(continued)
Pin Configurations
Pin Name Function
A0 - A16 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
I/O0 - I/O7
NC No Connect
DC Don’t Connec t
Data
Inputs/Outputs
PDIP
Top View
TSOP
Top View
PLCC
Top View
AT28C010 Com/Ind
Note: PLCC package pin 1
is a DON’T CONNECT.
2-231
Description (Continued)
The AT28C010 is accessed like a Static RAM for the read
or write cycle without the need for external components.
The device contains a 128-byte page register to allow writing of up to 128-bytes simultaneously. During a write cycle, the address and 1 to 128-bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device
will automatically write the latched data using an internal
control timer. The end of a write cycle can be detected by
DATA POLLING of I/O7. Once the end of a write cycle has
been detected a new access for a read or write can begin.
Block Diagram
Atmel’s 28C010 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correc tion for extended endurance and improved
data retention characteristics. An optional software data
protection mechanism is available to guard against inadvertent w rites. The device also includes an extra 128bytes of E
2
PROM for device identification or tracking.
Absolute Maximum Ratings*
Temperature Under Bias.................-55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
2-232 AT28C010 Com/Ind
+ 0.6V
CC
*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-
mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Device Operation
READ: The AT28C010 is accessed like a Static RAM.
CE and OE are low and WE is high, the data stored
When
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either
line control gives designers flexibility in preventing bus
contention in their system.
BYTE WRITE: A low pulse on the
WE low (respectively) and OE high initiates a write cy-
or
cle. The address is latched on the falling edge of
WE, whichever occurs last. The data is latched by the firs t
rising edge of
started it will automatically time itself to completion. Once
a programming operation has been initiated and for the
duration of t
ing operation.
PAGE WRITE: The page write operation of the AT28C010
allows 1 to 128-bytes of data to be written into the device
during a single internal programming period. A page write
operation is initiated in the same manner as a byte write;
the first byte written can then be followed by 1 to 127 additional bytes. Each successive byte must be written within
150 µs (t
ceeded the AT28C010 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page
as defined by the state of the A7 - A16 inputs. For each
WE high to low transition during the page write operation,
A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
DATA POLLING: The AT28C010 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complem ent of the written data to be presented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin.
write cycle.
TOGGLE BIT: In addition to
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
CE or WE. Once a byte write has been
, a read operation will effectively be a poll-
WC
) of the previous byte. If the t
BLC
DATA Polling may begin at anytime during the
CE or OE is high. This dual-
WE or CE input with CE
CE or
limit is ex-
BLC
DATA Polling the AT28C010
AT28C010 Com/Ind
DATA PROTECTION: If precautions are not taken, inad-
vertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware
and software features that will protect the memory agains t
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28C010 in the following ways: (a) V
write function is inhibited; (b) V
has reached 3.8V the device will automatically time
V
CC
out 5 ms (typical) before allowing a write: (c) write inhibit holding any one of
write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the
SOFTWARE DATA PROTECTION: A software controlled
data protection feature has been implemented on the
AT28C010. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C010 is
shipped from Atmel with SDP disabled.
SDP is enabled by the h ost system issuing a series of
three write co mmands; three specific bytes of data are
written to three specific addresses (refer to Software Data
Protection Algorithm). After writing the 3-byte command
sequence and after t
tected against inadvertent write operations. It should be
noted, that o nce protected the host may sti ll perform a
byte or page write to the AT28C010. This is done by preceding the data to be written by the same 3-byte command
sequence used to enable SDP.
Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28C010 during
power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in
either a byte or page write operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of t
polling operations.
sense - if VCC is below 3.8V (typical) the
CC
power-on delay - once
CC
OE low, CE high or WE high inhibits
WE or CE inputs will not initiate a write cycle.
the entire AT28C010 will be pro-
WC
, read operations will effectively be
WC
(continued)
2-233
Device Operation (Continued)
DEVICE IDENTIFICATION: An extra 128-bytes of
2
PROM memory are available to the user for device
E
identification. By raising A9 to 12V ± 0.5V and using ad-
OPTIONAL CHIP ERASE MODE: The entire device can
be erased using a 6-byte software code. Please see Soft-
ware Chip Erase application note for details.
dress locations 1FF80H to 1FFFFH the bytes may be written to or read from in the same manner as the regular
memory array.
DC and AC Operating Range
AT28C010-12 AT28C010-15 AT28C010-20
Operating
Temperature (Case)
V
Power Supply 5V ± 10% 5V ± 10% 5V ± 10%
CC
Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C
Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C
Operating Modes
Mode CE OE WE I/O
Read V
(2)
Write
Standby/Write Inhibit V
IL
V
IL
IH
Write Inhibit X X V
Write Inhibit X V
Output Disable X V
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
V
IL
V
IH
(1)
X
IL
IH
V
IH
V
IL
X High Z
IH
X
X High Z
D
D
OUT
IN
DC Characteristics
Symbol Parameter Condition Min Max Units
I
LI
I
LO
I
SB1
I
SB2
I
CC
V
IL
V
IH
V
OL
V
OH1
V
OH2
2-234 AT28C010 Com/Ind
Input Load Current VIN = 0V to VCC + 1V 10 µA
Output Leakage Current V
VCC Standby Current CMOS CE = V
= 0V to V
I/O
CC
CC
10 µA
- 0.3V to VCC + 1V 200 µA
VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA
V
Active Current f = 5 MHz; I
CC
= 0 mA 40 mA
OUT
Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA .45 V
Output High Voltage IOH = -400 µA 2.4 V
Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V
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