BDTIC www.BDTIC.com/ATMEL
Features
•
Fast Read Access Time – 120 ns
•
Automatic Page Write Operation
– Internal Address and Data Latches for 128 Bytes
– Internal Control Timer
•
Fast Write Cycle Time
– Page Write Cycle Time – 10 ms Maximum
– 1 to 128-byte Page Write Operation
•
Low Power Dissipation
– 40 mA Active Current
– 200 µA CMOS Standby Current
•
Hardware and Software Data Protection
•
DATA Polling for End of Write Detection
•
High Reliability CMOS Technology
– Endurance: 10
– Data Retention: 10 Years
•
Single 5V ± 10% Supply
•
CMOS and TTL Compatible Inputs and Outputs
•
JEDEC Approved Byte-wide Pinout
•
Industrial Temperature Ranges
•
Green (Pb/Halide-free) Packaging Option
4
or 105 Cycles
1-megabit
(128K x 8)
Paged Parallel
EEPROM
AT28C010
1. Description
The AT28C010 is a high-performance electrically-erasable and programmable readonly memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 120 ns with power dissipation of just 220 mW. When the device is
deselected, the CMOS standby current is less than 200 µA.
The AT28C010 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 128-byte page register to allow
writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to
128 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA
new access for a read or write can begin.
Atmel’s AT28C010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra
128 bytes of EEPROM for device identification or tracking.
polling of I/O7. Once the end of a write cycle has been detected a
0353G–PEEPR–10/06
AT28C010
2. Pin Configurations
Pin Name Function
A0 - A16 Addresses
CE Chip Enable
OE
WE
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect
2.1 32-lead TSOP Top View
A9
A8
NC
WE
NC
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A13
A14
VCC
A16
A15
A12
Output Enable
Write Enable
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
2.2 32-lead PDIP Top View
1
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
2.3 32-lead PLCC Top View
A12
A15
A16DCVCCWENC
432
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
13
I/O0
14151617181920
I/O1
Note: PLCC package pin 1 is Don’t Connect.
I/O2
GND
1
323130
I/O3
I/O4
I/O5
29
28
27
26
25
24
23
22
21
I/O6
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
0353G–PEEPR–10/06
2
3. Block Diagram
4. Device Operation
4.1 Read
The AT28C010 is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE
control gives designers flexibility in preventing bus contention in their system.
AT28C010
or OE is high. This dual-line
4.2 Byte Write
4.3 Page Write
4.4 DATA Polling
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a
write cycle. The address is latched on the falling edge of CE
The data is latched by the first rising edge of CE
will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of t
The page write operation of the AT28C010 allows 1 to 128 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 127 additional
bytes. Each successive byte must be written within 150 µs (t
t
limit is exceeded the AT28C010 will cease accepting data and commence the internal
BLC
programming operation. All bytes during a page write operation must reside on the same page
as defined by the state of the A7 - A16 inputs. For each WE
page write operation, A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within the page are to be written. The
bytes may be loaded in any order and may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary cycling of other bytes within the
page does not occur.
The AT28C010 features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O
valid on all outputs, and the next write cycle may begin. DATA
during the write cycle.
, a read operation will effectively be a polling operation.
WC
. Once the write cycle has been completed, true data is
7
or WE. Once a byte write has been started it
or WE, whichever occurs last.
) of the previous byte. If the
BLC
high to low transition during the
Polling may begin at anytime
0353G–PEEPR–10/06
3
4.5 Toggle Bit
In addition to DATA Polling the AT28C010 provides another method for determining the end of
a write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write
cycle.
4.6 Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel
the memory against inadvertent writes.
4.6.1 Hardware Protection
Hardware features protect against inadvertent writes to the AT28C010 in the following ways:
(a) V
CC
delay – once V
allowing a write; (c) write inhibit – holding any one of OE
cycles; and (d) noise filter—pulses of less than 15 ns (typical) on the WE
initiate a write cycle.
4.6.2 Software Data Protection
A software controlled data protection feature has been implemented on the AT28C010. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C010 is shipped from Atmel with SDP
disabled.
®
has incorporated both hardware and software features that will protect
sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on
has reached 3.8V the device will automatically time out 5 ms (typical) before
CC
low, CE high or WE high inhibits write
or CE inputs will not
SDP is enabled by the host system issuing a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after t
protected against inadvertent write operations. It should be noted, that once protected the host
may still perform a byte or page write to the AT28C010. This is done by preceding the data to
be written by the same 3-byte command sequence used to enable SDP.
Once set, SDP will remain active unless the disable command sequence is issued. Power
transitions do not disable SDP and SDP will protect the AT28C010 during power-up and
power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device
and the memory addresses used in the sequence may be written with data in either a byte or
page write operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence
will start the internal write timers. No data will be written to the device; however, for the duration of t
, read operations will effectively be polling operations.
WC
4.7 Device Identification
An extra 128 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V ± 0.5V and using address locations 1FF80H to 1FFFFH the bytes may be
written to or read from in the same manner as the regular memory array.
4.8 Optional Chip Erase Mode
The entire device can be erased using a 6-byte software code. Please see Software Chip
Erase application note for details.
the entire AT28C010 will be
WC
4
AT28C010
0353G–PEEPR–10/06
AT28C010
5. DC and AC Operating Range
AT28C010-12 AT28C010-15
Operating Temperature (Case)
V
Power Supply 5V ± 10% 5V ± 10%
CC
6. Operating Modes
Mode CE OE WE I/O
Read V
(2)
Write
Standby/Write Inhibit V
Write Inhibit X X V
Write Inhibit X V
Output Disable X V
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
7. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
Ind. -40°C - 85°C -40°C - 85°C
X
V
IL
V
IH
(1)
IL
IH
IL
V
IL
IH
V
IH
V
IL
X High Z
IH
X
X High Z
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
+ 0.6V
CC
D
OUT
D
IN
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
8. DC Characteristics
Symbol Parameter Condition Min Max Units
I
LI
I
LO
I
SB1
I
SB2
I
CC
V
IL
V
IH
V
OL
V
OH1
V
OH2
0353G–PEEPR–10/06
Input Load Current VIN = 0V to VCC + 1V 10 µA
Output Leakage Current V
VCC Standby Current CMOS CE = V
= 0V to V
I/O
CC
CC
10 µA
- 0.3V to VCC + 1V 200 µA
VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA
V
Active Current f = 5 MHz; I
CC
= 0 mA 40 mA
OUT
Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA 0.45 V
Output High Voltage IOH = -400 µA 2.4 V
Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V
5
9. AC Read Characteristics
Symbol Parameter
AT28C010-12 AT28C010-15
UnitsMin Max Min Max
t
t
t
t
t
ACC
CE
OE
DF
OH
(1)
(2)
(3)(4)
Address to Output Delay 120 150 ns
CE to Output Delay 120 150 ns
OE to Output Delay 0 50 0 55 ns
CE or OE to Output Float 0 50 0 55 ns
Output Hold from OE, CE or Address, Whichever
Occurred First
10. AC Read Waveforms
00ns
(1)(2)(3)(4)
Notes: 1. CE may be delayed up to t
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by t
without impact on t
3. t
is specified from OE or CE whichever occurs first (CL = 5 pF).
DF
ACC
.
4. This parameter is characterized and is not 100% tested.
- tCE after the address transition without impact on t
ACC
ACC
.
- tOE after an address change
ACC
6
AT28C010
0353G–PEEPR–10/06
11. Input Test Waveforms and Measurement Level
, tF < 5 ns
t
R
12. Output Test Load
13. Pin Capacitance
f = 1 MHz, T = 25°C
(1)
AT28C010
Symbol Typ Max Units Conditions
C
IN
C
OUT
Note: 1. This parameter is characterized and is not 100% tested.
410pFV
812pFV
IN
OUT
= 0V
= 0V
0353G–PEEPR–10/06
7
14. AC Write Characteristics
Symbol Parameter Min Max Units
, t
t
AS
OES
t
AH
t
CS
t
CH
t
WP
t
DS
t
, t
DH
OEH
Address, OE Set-up Time 0 ns
Address Hold Time 50 ns
Chip Select Set-up Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE)100ns
Data Set-up Time 50 ns
Data, OE Hold Time 0 ns
15. AC Write Waveforms
15.1 WE Controlled
15.2 CE
8
AT28C010
Controlled
0353G–PEEPR–10/06
AT28C010
t
t
V
16. Page Mode Characteristics
Symbol Parameter Min Max Units
t
WC
t
AS
t
AH
t
DS
t
DH
t
WP
t
BLC
t
WPH
Write Cycle Time 10 ms
Address Set-up Time 0 ns
Address Hold Time 50 ns
Data Set-up Time 50 ns
Data Hold Time 0 ns
Write Pulse Width 100 ns
Byte Load Cycle Time 150 µs
Write Pulse Width High 50 ns
17. Page Mode Write Waveforms
(1)(2)
Notes: 1. A7 through A16 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
18. Chip Erase Waveforms
= 5 µsec (min.)
S
= tH = 10 msec (min.)
W
= 12.0V ± 0.5V
H
9
0353G–PEEPR–10/06
19. Software Data Protection
Enable Algorithm
LOAD DATA AA
TO
ADDRESS 5555
(1)
20. Software Data Protection
Disable Algorithm
LOAD DATA AA
TO
ADDRESS 5555
(1)
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS
LOAD LAST BYTE
TO
LAST ADDRESS
WRITES ENABLED
(4)
ENTER DATA
PROTECT STATE
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Write Protect state will be activated at end of write
even if no other data is loaded.
3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.
4. 1 to 128 bytes of data are loaded.
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
(2)
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS
LOAD LAST BYTE
TO
LAST ADDRESS
EXIT DATA
PROTECT STATE
(4)
(3)
21. Software Protected Write Cycle Waveforms
(1)(2)(3)
Notes: 1. A0 through A14 must conform to the addressing sequence for the first 3 bytes as shown above.
2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7 - A16) must
be the same for each high to low transition of WE (or CE).
3. OE
must be high only when WE and CE are both low.
10
AT28C010
0353G–PEEPR–10/06
AT28C010
22. Data Polling Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
23. Data Polling Waveforms
ns
24. Toggle Bit Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
OEHP
t
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
OE High Pulse 150 ns
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
25. Toggle Bit Waveforms
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
ns
0353G–PEEPR–10/06
11
26. Ordering Information
(1)
26.1 Standard Package
I
t
ACC
(ns)
120 40 0.2
150 40 0.2
Note: 1. See “Valid Part Numbers” on page 13.
CC
(mA)
Ordering Code Package Operation RangeActive Standby
AT28C010(E)-12JI
AT28C010(E)-12PI
AT28C010(E)-12TI
AT28C010(E)-15JI
AT28C010(E)-15PI
AT28C010(E)-15TI
26.2 Green Package Option (Pb/Halide-free)
I
t
ACC
(ns)
120 40 0.2
150 40 0.2
CC
(mA)
Ordering Code Package Operation RangeActive Standby
AT28C010-12JU
AT28C010-12TU
AT28C010(E)-12JU
AT28C010(E)-12PU
AT28C010(E)-12TU
AT28C010-15JU
AT28C010-15TU
AT28C010(E)-15JU
AT28C010(E)-15PU
AT28C010(E)-15TU
32J
32P6
32T
32J
32P6
32T
32J
32T
32J
32P6
32T
32J
32T
32J
32P6
32T
Industrial
(-40° to 85° C)
Industrial
(-40° to 85° C)
Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32P6 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T
W
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
E High-endurance Option: Endurance = 100K Write Cycles
12
32-lead, Plastic Thin Small Outline Package (TSOP)
Die
Options
AT28C010
0353G–PEEPR–10/06
27. Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers Speed Package and Temperature Combinations
AT28C010 12 JI, JU, PI, TI, TU, PU
AT28C010E 12 JI, PI, TI, JU, PU, TU
AT28C010 15 JI, JU, PI, TI, TU, PU
AT28C010E 15 JI, PI, TI, JU, PU, TU
28. Die Products
Reference Section: Parallel EEPROM Die Products
AT28C010
0353G–PEEPR–10/06
13
29. Packaging Information
29.1 32J – PLCC
1.14(0.045) X 45˚
B
e
0.51(0.020)MAX
45˚ MAX (3X)
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
PIN NO. 1
IDENTIFIER
D1
D
D2
1.14(0.045) X 45˚
E1 E
0.318(0.0125)
0.191(0.0075)
E2
B1
A2
A1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2 9.906 – 10.922
E 14.859 – 15.113
E1 13.894 – 14.046 Note 2
E2 12.471 – 13.487
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
MIN
NOM
MAX
NOTE
10/04/01
14
2325 Orchard Parkway
R
San Jose, CA 95131
AT28C010
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
32J
0353G–PEEPR–10/06
REV.
B
29.2 32P6 – PDIP
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
AT28C010
D
e
0º ~ 15º
eB
Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
TITLE
2325 Orchard Parkway
R
San Jose, CA 95131
32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A – – 4.826
A1 0.381 – –
D 41.783 – 42.291 Note 1
E 15.240 – 15.875
E1 13.462 – 13.970 Note 1
B 0.356 – 0.559
B1 1.041 – 1.651
L 3.048 – 3.556
C 0.203 – 0.381
eB 15.494 – 17.526
e 2.540 TYP
MIN
NOM
MAX
DRAWING NO.
32P6
NOTE
09/28/01
REV.
B
0353G–PEEPR–10/06
15
29.3 32T – TSOP
PIN 1
Pin 1 Identifier
D1
D
e
E
b
A2
A
SEATING PLANE
A1
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
0º ~ 8º
L
COMMON DIMENSIONS
SYMBOL
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
c
L1
GAGE PLANE
(Unit of Measure = mm)
MIN
NOM
MAX
NOTE
16
2325 Orchard Parkway
R
San Jose, CA 95131
AT28C010
TITLE
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
32T
0353G–PEEPR–10/06
10/18/01
REV.
B
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