ATMEL AT28C010 User Manual

BDTIC www.BDTIC.com/ATMEL

Features

•Fast Read Access Time – 120 ns

•Automatic Page Write Operation

–Internal Address and Data Latches for 128 Bytes

–Internal Control Timer

•Fast Write Cycle Time

–Page Write Cycle Time – 10 ms Maximum

–1 to 128-byte Page Write Operation

•Low Power Dissipation

–40 mA Active Current

–200 µA CMOS Standby Current

•Hardware and Software Data Protection

•DATA Polling for End of Write Detection

•High Reliability CMOS Technology

–Endurance: 104 or 105 Cycles

–Data Retention: 10 Years

•Single 5V ± 10% Supply

•CMOS and TTL Compatible Inputs and Outputs

•JEDEC Approved Byte-wide Pinout

•Industrial Temperature Ranges

•Green (Pb/Halide-free) Packaging Option

1. Description

The AT28C010 is a high-performance electrically-erasable and programmable readonly memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 200 µA.

The AT28C010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin.

Atmel’s AT28C010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 128 bytes of EEPROM for device identification or tracking.

1-megabit

(128K x 8) Paged Parallel EEPROM

AT28C010

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AT28C010

2. Pin Configurations

2.2 32-lead PDIP Top View

Pin Name

Function

NC

1

32

VCC

A0 - A16

Addresses

A16

2

31

WE

A15

3

30

NC

CE

Chip Enable

A12

4

29

A14

Output Enable

OE

A7

5

28

A13

A6

6

27

A8

Write Enable

WE

A5

7

26

A9

I/O0 - I/O7

Data Inputs/Outputs

A4

8

25

A11

A3

9

24

NC

No Connect

OE

A2

10

23

A10

DC

Don’t Connect

A1

11

22

CE

A0

12

21

I/O7

I/O0

13

20

I/O6

I/O1

14

19

I/O5

I/O2

15

18

I/O4

GND

16

17

I/O3

2.132-lead TSOP Top View

A11				1	32				OE
	A9			2	31				A10
	A8			3	30
										CE
A13				4	29				I/O7
A14				5	28				I/O6
	NC			6	27				I/O5
				7	26				I/O4
	WE
VCC				8	25				I/O3
	NC			9	24				GND
A16				10	23				I/O2
A15				11	22				I/O1
A12				12	21				I/O0
	A7			13	20				A0
	A6			14	19				A1
	A5			15	18				A2
	A4			16	17				A3

2.332-lead PLCC Top View

	A12	A15	A16	DC	VCC		WE	NC
A7	4	3	2	1	32	31		30	A14
	5							29
A6	6							28	A13
A5	7							27	A8
A4	8							26	A9
A3	9							25	A11
A2	10							24
									OE
A1	11							23	A10
A0	12							22
									CE
I/O0	13	15	16	17	18	19		21	I/O7
	14							20
	I/O1	I/O2	GND	I/O3	I/O4		I/O5	I/O6

Note: PLCC package pin 1 is Don’t Connect.

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AT28C010

3. Block Diagram

4. Device Operation

4.1Read

The AT28C010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system.

4.2Byte Write

A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation.

4.3Page Write

The page write operation of the AT28C010 allows 1 to 128 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127 additional bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28C010 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page write operation, A7 - A16 must be the same.

The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.

4.4DATA Polling

The AT28C010 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is

valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle.

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4.5Toggle Bit

In addition to DATA Polling the AT28C010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.

4.6Data Protection

If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel® has incorporated both hardware and software features that will protect the memory against inadvertent writes.

4.6.1Hardware Protection

Hardware features protect against inadvertent writes to the AT28C010 in the following ways:

(a) VCC sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay – once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before

allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles; and (d) noise filter—pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle.

4.6.2Software Data Protection

A software controlled data protection feature has been implemented on the AT28C010. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C010 is shipped from Atmel with SDP disabled.

SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after tWC the entire AT28C010 will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28C010. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP.

Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28C010 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation.

After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations.

4.7Device Identification

An extra 128 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 1FF80H to 1FFFFH the bytes may be written to or read from in the same manner as the regular memory array.

4.8Optional Chip Erase Mode

The entire device can be erased using a 6-byte software code. Please see Software Chip

Erase application note for details.

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AT28C010

5. DC and AC Operating Range

		AT28C010-12	AT28C010-15
Operating Temperature (Case)	Ind.	-40°C - 85°C	-40°C - 85°C
VCC Power Supply		5V ± 10%	5V ± 10%

6.

Operating Modes

Mode

I/O

CE

OE

WE

Read

VIL

VIL

VIH

DOUT

Write(2)

V

V

IH

V

IL

D

IN

IL

Standby/Write Inhibit

VIH

X(1)

X

High Z

Write Inhibit

X

X

VIH

Write Inhibit

X

VIL

X

Output Disable

X

VIH

X

High Z

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.

7.

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Temperature Under Bias................................

-55°C to +125°C

Maximum Ratings” may cause permanent dam-

Storage Temperature .....................................

-65°C to +150°C

age to the device. This is a stress rating only and

functional operation of the device at these or any

All Input Voltages

other conditions beyond those indicated in the

(including NC Pins)

operational sections of this specification is not

with Respect to Ground ...................................

-0.6V to +6.25V

implied. Exposure to absolute maximum rating

All Output Voltages

conditions for extended periods may affect

-0.6V to VCC + 0.6V

device reliability

with Respect to Ground .............................

Voltage on

and A9

OE

with Respect to Ground ...................................

-0.6V to +13.5V

8. DC Characteristics

Symbol	Parameter	Condition			Min	Max	Units
ILI	Input Load Current	VIN = 0V to VCC + 1V				10	A
ILO	Output Leakage Current	VI/O = 0V to VCC				10	A
ISB1	VCC Standby Current CMOS			= VCC - 0.3V to VCC + 1V		200	A
			CE
ISB2	VCC Standby Current TTL			= 2.0V to VCC + 1V		3	mA
			CE
ICC	VCC Active Current		f = 5 MHz; IOUT = 0 mA			40	mA
VIL	Input Low Voltage					0.8	V
VIH	Input High Voltage				2.0		V
VOL	Output Low Voltage	IOL = 2.1 mA				0.45	V
VOH1	Output High Voltage	IOH = -400 µA			2.4		V
VOH2	Output High Voltage CMOS	IOH = -100 µA; VCC = 4.5V			4.2		V

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