ATMEL AT28C010 User Manual

BDTIC www.BDTIC.com/ATMEL

Features

•

Fast Read Access Time – 120 ns

•

Automatic Page Write Operation

– Internal Address and Data Latches for 128 Bytes – Internal Control Timer

•

Fast Write Cycle Time

– Page Write Cycle Time – 10 ms Maximum – 1 to 128-byte Page Write Operation

•

Low Power Dissipation

– 40 mA Active Current – 200 µA CMOS Standby Current

•

Hardware and Software Data Protection

•

DATA Polling for End of Write Detection

•

High Reliability CMOS Technology

– Endurance: 10 – Data Retention: 10 Years

•

Single 5V ± 10% Supply

•

CMOS and TTL Compatible Inputs and Outputs

•

JEDEC Approved Byte-wide Pinout

•

Industrial Temperature Ranges

•

Green (Pb/Halide-free) Packaging Option

or 105 Cycles

1-megabit (128K x 8) Paged Parallel EEPROM

AT28C010

1. Description

The AT28C010 is a high-performance electrically-erasable and programmable readonly memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 200 µA.

The AT28C010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA new access for a read or write can begin.

Atmel’s AT28C010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 128 bytes of EEPROM for device identification or tracking.

polling of I/O7. Once the end of a write cycle has been detected a

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AT28C010

2. Pin Configurations

Pin Name Function

A0 - A16 Addresses

CE Chip Enable

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

DC Don’t Connect

2.1 32-lead TSOP Top View

A9 A8

A7 A6 A5 A4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A11

A13 A14

VCC

A16 A15 A12

Output Enable

Write Enable

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3

2.2 32-lead PDIP Top View

NC A16 A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 I/O0 I/O1 I/O2

GND

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3

2.3 32-lead PLCC Top View

A12

A15

A16DCVCCWENC

432

I/O0

14151617181920

I/O1

Note: PLCC package pin 1 is Don’t Connect.

I/O2

GND

323130

I/O3

I/O4

I/O5

29 28 27 26 25 24 23 22 21

I/O6

A14 A13 A8 A9 A11 OE A10 CE I/O7

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3. Block Diagram

4. Device Operation

4.1 Read

The AT28C010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE control gives designers flexibility in preventing bus contention in their system.

AT28C010

or OE is high. This dual-line

4.2 Byte Write

4.3 Page Write

4.4 DATA Polling

A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE The data is latched by the first rising edge of CE will automatically time itself to completion. Once a programming operation has been initiated and for the duration of t

The page write operation of the AT28C010 allows 1 to 128 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127 additional bytes. Each successive byte must be written within 150 µs (t t

limit is exceeded the AT28C010 will cease accepting data and commence the internal

BLC

programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE page write operation, A7 - A16 must be the same.

The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.

The AT28C010 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O valid on all outputs, and the next write cycle may begin. DATA during the write cycle.

, a read operation will effectively be a polling operation.

. Once the write cycle has been completed, true data is

or WE. Once a byte write has been started it

or WE, whichever occurs last.

) of the previous byte. If the

BLC

high to low transition during the

Polling may begin at anytime

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4.5 Toggle Bit

In addition to DATA Polling the AT28C010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.

4.6 Data Protection

If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel the memory against inadvertent writes.

4.6.1 Hardware Protection

Hardware features protect against inadvertent writes to the AT28C010 in the following ways: (a) V

delay – once V allowing a write; (c) write inhibit – holding any one of OE cycles; and (d) noise filter—pulses of less than 15 ns (typical) on the WE initiate a write cycle.

4.6.2 Software Data Protection

A software controlled data protection feature has been implemented on the AT28C010. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C010 is shipped from Atmel with SDP disabled.

has incorporated both hardware and software features that will protect

sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on

has reached 3.8V the device will automatically time out 5 ms (typical) before

low, CE high or WE high inhibits write

or CE inputs will not

SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after t protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28C010. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP.

Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28C010 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation.

After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of t

, read operations will effectively be polling operations.

4.7 Device Identification

An extra 128 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 1FF80H to 1FFFFH the bytes may be written to or read from in the same manner as the regular memory array.

4.8 Optional Chip Erase Mode

The entire device can be erased using a 6-byte software code. Please see Software Chip Erase application note for details.

the entire AT28C010 will be

AT28C010

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AT28C010

5. DC and AC Operating Range

AT28C010-12 AT28C010-15

Operating Temperature (Case)

Power Supply 5V ± 10% 5V ± 10%

6. Operating Modes

Mode CE OE WE I/O

Read V

(2)

Write

Standby/Write Inhibit V

Write Inhibit X X V

Write Inhibit X V

Output Disable X V

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.

7. Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

Ind. -40°C - 85°C -40°C - 85°C

(1)

X High Z

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

+ 0.6V

OUT

Voltage on OE and A9

with Respect to Ground ...................................-0.6V to +13.5V

8. DC Characteristics

Symbol Parameter Condition Min Max Units

SB1

SB2

OH1

OH2

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Input Load Current VIN = 0V to VCC + 1V 10 µA

Output Leakage Current V

VCC Standby Current CMOS CE = V

= 0V to V

I/O

10 µA

- 0.3V to VCC + 1V 200 µA

VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA

Active Current f = 5 MHz; I

= 0 mA 40 mA

OUT

Input Low Voltage 0.8 V

Input High Voltage 2.0 V

Output Low Voltage IOL = 2.1 mA 0.45 V

Output High Voltage IOH = -400 µA 2.4 V

Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

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