The AT27LV512A is a high performance, low power, low voltage 524,288 bit one-time
programmable read only memory (OTP EPROM) organized as 64K by 8 bits. It requires only one supply in the range of 3.0V to 3.6V in normal read mode operation,
making it ideal for fast, portable systems using battery power.
Atmel’s innovative design techniques provide fast speeds that rival 5V parts while
keeping the low power consumption of a 3.3V supply. At V
accessed in less than 90 ns. With a typical power dissipation of only 18 mW at 5 MHz
and V
ard 5V EPROM.
= 3.3V, the AT27LV512A consumes less than one fifth the power of a stand-
Note: PLCC Package Pins 1 and 17
are DON’T CONNECT.
TSOP Top View
Type 1
3-85
Description (Continued)
Standby mode supply current is typically less than 1 µA at
3.3V.
The AT27LV512A is available in industry standard
JEDEC-approved one-time programmable (OTP) plastic
PLCC, SOIC, and TSOP packages. All devices feature
two-line control (
prevent bus contention.
The AT27LV512A operating with V
TTL level outputs that are compatible with standard TTL
logic devices operating at V
capable of standard 5-volt operation making it ideally
suited for dual supply range systems or card products that
are pluggable in both 3-volt and 5-volt hosts.
Atmel’s AT27LV512A has additional features to ensure
high quality and efficient production use. The Rapid
gramming Algorithm reduces the time required to program
the part and guarantees reliable programming. Programming time i s typically only 100 µs/byte. The Integrated
Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry
standard programming equipment to select the proper
programming algorithms and voltages. The AT27LV512A
programs exactly the same way as a standard 5V
AT27C512R and uses the same programming equipment.
CE, OE) to give designers the flexibility to
at 3.0V produces
CC
= 5.0V. The device is also
CC
Pro-
System Considerations
Switching between active and standby conditions via the
Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these
transients may exceed data sheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor
should be utilized for each device. This capacitor should
be connected between the V
the device, as close to the device as possible. Additionally,
to stabilize the supply voltage level on printed circuit
boards with large EPROM arrays, a 4.7 µF bulk electrolytic
capacitor should be utilized, again connected between the
and Ground terminals. This capacitor should be posi-
V
CC
tioned as close as possible to the point where the power
supply is connected to the array.
and Ground terminals of
CC
3-86AT27LV512A
AT27LV512A
Block Diagram
Absolute Maximum Ra ti ngs *
Temperature Under Bias .................. -40°C to +85°C
Storage Temperature...................... -65°C to +125°C
Voltage on Any Pin with
Respect to Ground.........................-2.0V to +7.0V
Voltage on A9 with
Respect to Ground ......................-2.0V to +14.0V
VPP Supply Voltage with
Respect to Ground.......................-2.0V to +14.0V
*NOTICE: Stresses beyond those listed unde r “Absolu te Maxi-
mum Ratings” may cause permanent da ma ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
(1)
(1)
(1)
Operating Modes
Mode \ Pin
(2)
Read
Output Disable
Standby
Rapid Program
PGM Inhibit
Product Identification
Notes: 1. X can be VIL or VIH.
2. Read, output disable, and standby modes
3. Refer to Programming Characteristics. Programming
Note: 1. Minimum voltage is -0.6V dc which may undershoot to -
2.0V for pulses of less than 20 ns. Maximum outpu t
+ 0.75V dc which may be ex-
CC
CC
VCC
CC
CC
VCC
(2)
(2)
(2)
(3)
(3)
(3)
Outputs
D
OUT
High Z
High Z
D
IN
High Z
Identification
Code
IH
pin voltage is V
ceeded if certain precautions are observed (consult
application notes) and which may overshoot to +7.0
volts for pulses of less than 20 ns.
PP
IL
AiV
AiVCC
(1)
X
AiVCC
XV
A9 = VH
IL
A0 = VIH or VIL
A1 - A15 = V
4. VH = 12.0 ± 0.5V.
5. Two identifier by tes may be selected. All Ai inputs are held
low (VIL), except A9 which is set to VH and A0 which is toggled low (V
and high (V
(4)
IL
) to select the Manuf ac tu rer’s Identifi ca ti on byte
IL
) to select the Dev ice Code byte.
IH
3-87
DC and AC Operating Conditions f or Read Operation
Input Load CurrentVIN = VIL, V
Input Low Lev el-0.60.8V
Input High Level2.0VCC + 0.5V
Output Low VoltageI
Output High Volta geI
VCC Supply Current (Program and Verify)25mA
OE/VPP CurrentCE = V
A9 Product Identi fication Voltage11.512.5V
= 2.1 mA0.4V
OL
= -400 µA2.4V
OH
IH
IL
Min
Limits
Max
10µA
25mA
Units
3-91
AC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, OE/VPP = 13.0 ± 0.25 V
SymbolParam ete r
Address Setup Time2µs
t
AS
OE/VPP Setup Time2µs
t
OES
OE/VPP Hold Time2µs
t
OEH
Data Setup Time2µs
t
DS
Address Hold Time0µs
t
AH
Data Hold Time2µs
t
DH
CE High to
t
DFP
Output Float Delay
VCC Setup Time2µ s
t
VCS
CE Program Pulse Width
t
PW
Data Valid from CE
t
DV
OE/VPP Recovery Time2µs
t
VR
OE/VPP Pulse Rise
t
PRT
Time During Programming
*AC Conditions of Test:
Input Rise and Fa ll Times (10% to 90%)......... .. ..20 ns
Input Pulse Levels..................................0.45V to 2.4V
Input Timing Reference Level.................0.8V to 2.0V
Output Timing Reference Level..............0.8V to 2.0V
Test
Conditions*
(2)
(3)
(2)
(1)
Limits
MinMax
0130ns
95105µs
50ns
Units
1µs
Rapid Programming Algor ithm
A 100 µs CE pulse width is used to program. The address
is set to the first location. V
OE/VPP is raised to 13.0V. Each address is first programmed with one 100 µs
Then a verification / reprogramming loop is executed for
each address. In the event a byte fails to pass verification,
up to 10 successive 100 µs pulses are applied with a verification after each pulse. If the byte fails to verify after 10
pulses have been applied, the part is considered failed.
After the byte ve rifies properly, the next address is selected until all have been checked.
ered to V
and VCC to 5.0V. All bytes are read again and
IL
compared with the original data to determine if the device
passes or fails.
is raised to 6.5V and
CC
CE pulse without verification.
OE/VPP is then low-
Notes: 1. V
Atmel’s 27LV512 A Inte grated
Product Identification Code
Codes
Manufacturer0000111101E
Device Type 1000001010D
Note:1. The AT27LV512A has the same Product Identification
must be applied simultaneou sl y or before
CC
OE/VPP and removed simultaneously or after
OE/VPP.
2. This parameter is only sampl ed and is not 100%
tested. Output Float is defined as the point where
data is no longer driven —see timing diagram.
3. Program Pulse width tolerance is 100
Pins
A0 O7 O6 O5 O4 O3 O2 O1 O0
Code as the AT27C512R. Both are programming
compatible.
µsec ± 5%.
(1)
Hex
Data
3-92AT27LV512A
Ordering Information
AT27LV512A
t
ACC
(ns)
9080.02AT27LV512A-90JC32JCommercial
12080.02AT27LV512A-12JC32JCommercial
15080.02AT27LV512A-15JC32JCommercial
I
(mA)
CC
ActiveStandby
80.02AT27LV512A-90JI32JIndustrial
80.02AT27LV512A-12JI32JIndustrial
80.02AT27LV512A-15JI32JIndustrial
Ordering CodePackageOperation Range
AT27LV512A-90RC28R(0°C to 70°C)
AT27LV512A-90TC28T
AT27LV512A-90RI28R(-40°C to 85°C)
AT27LV512A-90TI28T
AT27LV512A-12RC28R(0°C to 70°C)
AT27LV512A-12TC28T
AT27LV512A-12RI28R(-40°C to 85°C)
AT27LV512A-12TI28T
AT27LV512A-15RC28R(0°C to 70°C)
AT27LV512A-15TC28T
AT27LV512A-15RI28R(-40°C to 85°C)
AT27LV512A-15TI28T
Package Type
32J32 Lead, Plastic J-Leaded Chip Carrier (PLCC)
28R28 Lead, 0.330" Wide, Pla stic Gull Wing S mall Outl in e (SOIC)
28T28 Lead, Thin Small Outline Package (TSOP)
3-93
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