ATMEL AT27LV256A User Manual

BDTIC www.BDTIC.com/ATMEL

Features

Fast Read Access Time – 55 ns
Dual Voltage Range Operation
– Low-voltage Power Supply Range, 3.0V to 3.6V
or Standard 5V ± 10% Supply Range
Pin Compatible with JEDEC Standard AT27C256R
Low-power CMOS Operation
– 20 µA Max (Less than 1 µA Typical) Standby for V – 29 mW Max Active at 5 MHz for V
JEDEC Standard Packages
– 32-lead PLCC – 28-lead SOIC – 28-lead TSOP
High-reliability CMOS Technology
– 2,000V ESD Protection – 200 mA Latchup Immunity
Rapid Programming Algorithm – 100 µs/Byte (Typical)
CMOS and TTL Compatible Inputs and Outputs
– JEDEC Standard for LVTTL
Integrated Product Identification Code
Industrial Temperature Range
Green (Pb/Halide-free) Packaging Option
= 3.6V
CC
= 3.6V
256K (32K x 8) Low-voltage OTP EPROM
AT27LV256A

1. Description

The AT27LV256A is a high-performance, low-power, low-voltage 262,144-bit one­time programmable read-only memory (OTP EPROM) organized as 32K by 8 bits. It requires only one supply in the range of 3.0V to 3.6V in normal read mode operation, making it ideal for fast, portable systems using battery power.
Atmel’s innovative design techniques provide fast speeds that rival 5V parts while keeping the low power consumption of a 3.3V supply. At V accessed in less than 55 ns. With a typical power dissipation of only 18 mW at 5 MHz and V dard 5V EPROM. Standby mode supply current is typically less than 1 µA at 3.3V.
The AT27LV256A is available in industry-standard JEDEC-approved one-time programmable (OTP) plastic PLCC, SOIC and TSOP packages. All devices feature two-line control (CE
The AT27LV256A operating with V compatible with standard TTL logic devices operating at V also capable of standard 5-volt operation making it ideally suited for dual supply range systems or card products that are pluggable in both 3-volt and 5-volt hosts.
Atmel’s AT27LV256A has additional features to ensure high quality and efficient pro­duction use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages. The AT27LV256A programs exactly the same way as a standard 5V AT27C256R and uses the same programming equipment.
= 3.3V, the AT27LV256A consumes less than one fifth the power of a stan-
CC
, OE) to give designers the flexibility to prevent bus contention.
at 3.0V produces TTL level outputs that are
CC
= 3.0V, any byte can be
CC
= 5.0V. The device is
CC
0547G–EPROM–12/07

2. Pin Configurations

Pin Name Function
A0 - A14 Addresses
O0 - O7 Outputs
CE
OE
NC No Connect
Chip Enable
Output Enable
AT27LV256A

2.1 28-lead SOIC Top View

VPP
A12
A7 A6 A5 A4 A3 A2 A1
A0 O0 O1 O2
GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15

2.2 32-lead PLCC Top View

A7
A12
A6 A5 A4 A3 A2 A1 A0
NC
O0
VPPNCVCC
432
5 6 7 8 9 10 11 12 13
14151617181920
1
323130
A14
A13
29 28 27 26 25 24 23 22 21
VCC A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3
A8 A9 A11 NC OE A10 CE O7 O6

2.3 28-lead TSOP (Type 1) Top View

22
OE
A11
A9
A8 A13 A14
VCC
VPP
A12
A7
A6
A5
A4
A3
23 24 25 26 27 28 1 2 3 4 5 6 7
21 20 19 18 17 16 15 14 13 12 11 10
A10 CE O7 O6 O5 O4 O3 GND O2 O1 O0 A0
9
A1
8
A2
O1
O2
GND
O3O4O5
NC
Note: 1. PLCC Package Pins 1 and 17 are Don’t Connect.
0547G–EPROM–12/07
2

3. System Considerations

Switching between active and standby conditions via the Chip Enable pin may produce tran­sient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the V to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the V close as possible to the point where the power supply is connected to the array.

4. Block Diagram

AT27LV256A
and Ground terminals of the device, as close
CC
and Ground terminals. This capacitor should be positioned as
CC

5. Absolute Maximum Ratings*

Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +125°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on A9 with
Respect to Ground ......................................-2.0V to +14.0V
VPP Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V
Note: 1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
V
+ 0.75V DC which may be exceeded if certain precautions are observed (consult application notes) and which may
overshoot to +7.0V for pulses of less than 20 ns.
(1)
(1)
(1)
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
0547G–EPROM–12/07
3

6. Operating Modes

Mode/Pin CE OE Ai V
(2)
Read
Output Disable
Standby
Rapid Program
PGM Verify
(2)
(2)
(3)
(3)
Optional PGM Verify
PGM Inhibit
(3)
Product Identification
(3)
(3)(5)
V
V
V
V
X
V
V
V
IL
IL
IH
IL
(1)
IL
IH
IL
V
V
X
V
V
V
V
V
IL
IH
(1)
IH
IL
IL
IH
IL
Ai V
(1)
X
(1)
X
Ai V
Ai V
Ai V
(1)
X
A9 = V
(4)
H
A0 = VIH or VIL A1 - A14 = V
IL
V
PP
CC
V
CC
V
CC
PP
PP
CC
V
PP
CC
Notes: 1. X can be VIL or VIH.
2. Read, output disable, and standby modes require, 3.0V ≤ V
≤ 3.6V, or 4.5V ≤ VCC ≤ 5.5V.
3. Refer to Programming Characteristics. Programming modes require VCC = 6.5V.
4. V
= 12.0 ± 0.5V.
H
5. Two identifier bytes may be selected. All Ai inputs are held low (V low (V
) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
IL
), except A9 which is set to VH and A0 which is toggled
IL

7. DC and AC Operating Conditions for Read Operation

V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
Outputs
D
OUT
High Z
High Z
D
IN
D
OUT
D
OUT
High Z
Identification Code
AT27LV256A
-55 -90
Industrial Operating Temperature (Case) -40°C - 85°C -40°C - 85°C
3.0V to 3.6V 3.0V to 3.6V
V
Power Supply
5V ± 10% 5V ± 10%
4
AT27LV256A
0547G–EPROM–12/07
AT27LV256A

8. DC and Operating Characteristics for Read Operation

Symbol Parameter Condition Min Max Units
= 3.0V to 3.6V
V
I
LI
I
LO
(2)
I
PP1
I
SB
I
V
IL
V
IH
V
OL
V
OH
= 4.5V to 5.5V
V
I
LI
I
LO
(2)
I
PP1
I
SB
I
V
IL
V
IH
V
OL
V
OH
Notes: 1. VCC must be applied simultaneously with or before VPP, and removed simultaneously with or after VPP.
Input Load Current VIN = 0V to V
Output Leakage Current V
(1)
V
Read/Standby Current VPP = V
PP
(1)
V
Standby Current
= 0V to V
OUT
CC
I
(CMOS), CE = V
SB1
(TTL), CE = 2.0 to VCC + 0.5V 100 µA
I
SB2
VCC Active Current f = 5 MHz, I
CC
CC ±
= 0 mA, CE = V
OUT
0.3V 20 µA
IL
±A
±A
10 µA
8mA
Input Low Voltage -0.6 0.8 V
Input High Voltage 2.0 VCC + 0.5 V
Output Low Voltage IOL = 2.0 mA 0.4 V
Output High Voltage IOH = -2.0 mA 2.4 V
Input Load Current VIN = 0V to V
Output Leakage Current V
(1)
V
Read/Standby Current VPP = V
PP
(1)
V
Standby Current
= 0V to V
OUT
CC
I
(CMOS), CE = VCC ± 0.3V 100 µA
SB1
(TTL), CE = 2.0 to VCC + 0.5V 1 mA
I
SB2
VCC Active Current f = 5 MHz, I
CC
= 0 mA, CE = V
OUT
IL
±A
±A
10 µA
20 mA
Input Low Voltage -0.6 0.8 V
Input High Voltage 2.0 VCC + 0.5 V
Output Low Voltage IOL = 2.1 mA 0.4 V
Output High Voltage IOH = -400 µA 2.4 V
2. V
may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
PP
0547G–EPROM–12/07
5

9. AC Characteristics for Read Operation

VCC = 3.0V to 3.6V and 4.5V to 5.5V
Symbol Parameter Condition
(3)
t
t
t
t
t
ACC
CE
OE
DF
OH
(2)
(2)(3)
(4)(5)
Address to Output Delay CE = OE = V
CE to Output Delay OE = V
OE to Output Delay CE = V
IL
IL
OE or CE High to Output Float, Whichever Occurred First
Output Hold from Address, CE or OE, Whichever Occurred First
AT27LV256A
-55 -90
Max Min Min Max
IL
55 90 ns
Units
55 90 ns
35 50 ns
30 40 ns
00ns
10. AC Waveforms for Read Operation
(1)
Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE
may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE may be delayed up to t
- tOE after the address is valid without impact on t
ACC
ACC
.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
6
AT27LV256A
0547G–EPROM–12/07

11. Input Test Waveforms and Measurement Levels

tR, tF < 20 ns (10% to 90%)

12. Output Test Load

AT27LV256A
Note: CL = 100 pF including jig capacitance.

13. Pin Capacitance

f = 1 MHz, T = 25°C
Symbol Typ Max Units Conditions
C
IN
C
OUT
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
(1)
48pFV
812pFV
IN
OUT
= 0V
= 0V
0547G–EPROM–12/07
7
14. Programming Waveforms
(1)
Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and t
3. When programming the AT27LV256A a 0.1 µF capacitor is required across V transients.
are characteristics of the device but must be accommodated by the programmer.
DFP
and ground to suppress spurious voltage
PP
8
AT27LV256A
0547G–EPROM–12/07

15. DC Programming Characteristics

TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Symbol Parameter Test Conditions
AT27LV256A
Limits
UnitsMin Max
I
V
V
V
V
I
I
V
LI
IL
IH
OL
OH
CC2
PP2
ID
Input Load Current VIN = VIL, V
IH
Input Low Level -0.6 0.8 V
Input High Level 2.0 VCC + 0.5 V
Output Low Voltage IOL = 2.1 mA 0.4 V
Output High Voltage I
= -400 µA 2.4 V
OH
VCC Supply Current (Program and Verify) 25 mA
VPP Current CE = V
IL
A9 Product Identification Voltage 11.5 12.5 V

16. AC Programming Characteristics

TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Symbol Parameter Test Conditions
t
AS
t
OES
t
DS
t
AH
t
t
DFP
t
VPS
t
VCS
t
PW
t
OE
t
PRT
Address Setup Time
OE Setup Time 2 µs
Input Rise and Fall Times:
Data Setup Time 2 µs
Address Hold Time 0 µs
Input Pulse Levels:
Data Hold Time 2 µs
OE High to Output Float Delay
VPP Setup Time 2 µs
(2)
Input Timing Reference Level:
VCC Setup Time 2 µs
CE Program Pulse Width
Data Valid from OE
(3)
(2)
Output Timing Reference Level:
VPP Pulse Rise Time During Programming 50 ns
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven – see timing diagram.
3. Program Pulse width tolerance is 100
µsec ± 5%.
(1)
s
(10% to 90%) 20 ns
0.45V to 2.4V 0 130 ns
0.8V to 2.0V
95 105 µs
0.8V to 2.0V
±10 µA
25 mA
Limits
UnitsMin Max
150 ns
17. Atmel’s AT27LV256A Integrated Product Identification Code
Pins
Codes
(1)
Hex
DataA0 O7 O6 O5 O4 O3 O2 O1 O0
Manufacturer 000011110 1E
Device Type 110001100 8C
Note: 1. The AT27LV256A has the same Product Identification Code as the AT27C256R. Both are programming compatible.
9
0547G–EPROM–12/07

18. Rapid Programming Algorithm

A 100 µs CE pulse width is used to program. The address is set to the first location. VCC is raised to 6.5V and V CE
pulse without verification. Then a verification/reprogramming loop is executed for each address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is considered failed. After the byte verifies properly, the next address is selected until all have been checked. V are read again and compared with the original data to determine if the device passes or fails.
is raised to 13.0V. Each address is first programmed with one 100 µs
PP
is then lowered to 5.0V and VCC to 5.0V. All bytes
PP
10
AT27LV256A
0547G–EPROM–12/07

19. Ordering Information

19.1 Standard Package

I
t
ACC
(ns)
55 8 0.02 AT27LV256A-55JI
90 8 0.02 AT27LV256A-90JI
CC
(mA)
Ordering Code Package Operation RangeActive Standby
AT27LV256A-55RI AT27LV256A-55TI
AT27LV256A-90RI AT27LV256A-90TI
32J 28R 28T
32J 28R 28T
AT27LV256A
(1)
(1)
Industrial
(-40° C to 85° C)
Industrial
(-40° C to 85° C)
Note:
Not recommended for new designs. Use Green package option.

19.2 Green Package Option (Pb/Halide-free)

I
t
ACC
(ns)
55 8 0.02 AT27LV256A-55JU
90 8 0.02 AT27LV256A-90JU
Note: 1. The 28-pin SOIC package is not recommended for new designs.
CC
(mA)
Ordering Code Package Operation RangeActive Standby
AT27LV256A-55RU AT27LV256A-55TU
AT27LV256A-90RU AT27LV256A-90TU
32J 28R 28T
32J 28R 28T
(1)
(-40° C to 85° C)
Industrial
Industrial
(1)
(-40° C to 85° C)
Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
28R 28-lead, 0.330" Wide, Plastic Gull Wing Small Outline (SOIC)
28T 28-lead, Thin Small Outline Package (TSOP)
0547G–EPROM–12/07
11

20. Packaging Information

20.1 32J – PLCC
1.14(0.045) X 45˚
B
e
0.51(0.020)MAX
45˚ MAX (3X)
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
PIN NO. 1 IDENTIFIER
D1
D
D2
1.14(0.045) X 45˚
E1 E
0.318(0.0125)
0.191(0.0075)
E2
B1
A2
A1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A 3.175 3.556
A1 1.524 2.413
A2 0.381
D 12.319 12.573
D1 11.354 11.506 Note 2
D2 9.906 10.922
E 14.859 15.113
E1 13.894 14.046 Note 2
E2 12.471 13.487
B 0.660 0.813
B1 0.330 0.533
e 1.270 TYP
MIN
NOM
MAX
NOTE
10/04/01
12
2325 Orchard Parkway
R
San Jose, CA 95131
AT27LV256A
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
32J
0547G–EPROM–12/07
REV.
B
20.2 28R – SOIC
AT27LV256A
B
E
1
PIN 1
e
D
A
1
0º ~ 8º
C
L
Note: 1. Dimensions D and E1 do not include mold Flash or protrusion. Mold Flash or protrusion shall not exceed
0.25 mm (0.010").
E
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A 2.39 – 2.79
A1 0.050 0.356
D 18.00 – 18.50 Note 1
E 11.70 12.50
E1 8.59 – 8.79 Note 1
B 0.356 – 0.508
C 0.203 0.305
L 0.94 1.27
e 1.27 TYP
MIN
NOM
MAX
NOTE
2325 Orchard Parkway
R
San Jose, CA 95131
0547G–EPROM–12/07
TITLE 28R, 28-lead, 0.330" Body Width,
Plastic Gull Wing Small Outline (SOIC)
5/18/2004
DRAWING NO.
28R
REV.
C
13
20.3 28T – TSOP
PIN 1
Pin 1 Identifier Area
D1
D
e
E
b
A2
A
A1
Notes: 1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
0º ~ 5º
SEATING PLANE
SYMBOL
c
L
L1
GAGE PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
A 1.20
A1 0.05 0.15
A2 0.90 1.00 1.05
D 13.20 13.40 13.60
D1 11.70 11.80 11.90 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 0.21
e 0.55 BASIC
NOM
MAX
NOTE
14
2325 Orchard Parkway
R
San Jose, CA 95131
AT27LV256A
TITLE
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
28T
0547G–EPROM–12/07
12/06/02
REV.
C
Loading...