ATMEL AT27LV256A User Manual
BDTIC www.BDTIC.com/ATMEL
Features
•Fast Read Access Time – 55 ns
•Dual Voltage Range Operation
–Low-voltage Power Supply Range, 3.0V to 3.6V or Standard 5V ± 10% Supply Range
•Pin Compatible with JEDEC Standard AT27C256R
•Low-power CMOS Operation
–20 µA Max (Less than 1 µA Typical) Standby for VCC = 3.6V
–29 mW Max Active at 5 MHz for VCC = 3.6V
•JEDEC Standard Packages
–32-lead PLCC
–28-lead SOIC
–28-lead TSOP
•High-reliability CMOS Technology
–2,000V ESD Protection
–200 mA Latchup Immunity
•Rapid Programming Algorithm – 100 µs/Byte (Typical)
•CMOS and TTL Compatible Inputs and Outputs
–JEDEC Standard for LVTTL
•Integrated Product Identification Code
•Industrial Temperature Range
•Green (Pb/Halide-free) Packaging Option
1. Description
The AT27LV256A is a high-performance, low-power, low-voltage 262,144-bit onetime programmable read-only memory (OTP EPROM) organized as 32K by 8 bits. It requires only one supply in the range of 3.0V to 3.6V in normal read mode operation, making it ideal for fast, portable systems using battery power.
Atmel’s innovative design techniques provide fast speeds that rival 5V parts while keeping the low power consumption of a 3.3V supply. At VCC = 3.0V, any byte can be accessed in less than 55 ns. With a typical power dissipation of only 18 mW at 5 MHz and VCC = 3.3V, the AT27LV256A consumes less than one fifth the power of a standard 5V EPROM. Standby mode supply current is typically less than 1 µA at 3.3V.
The AT27LV256A is available in industry-standard JEDEC-approved one-time programmable (OTP) plastic PLCC, SOIC and TSOP packages. All devices feature two-line control (CE, OE) to give designers the flexibility to prevent bus contention.
The AT27LV256A operating with VCC at 3.0V produces TTL level outputs that are compatible with standard TTL logic devices operating at VCC = 5.0V. The device is also capable of standard 5-volt operation making it ideally suited for dual supply range systems or card products that are pluggable in both 3-volt and 5-volt hosts.
Atmel’s AT27LV256A has additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages. The AT27LV256A programs exactly the same way as a standard 5V AT27C256R and uses the same programming equipment.
256K (32K x 8) Low-voltage OTP EPROM
AT27LV256A
0547G–EPROM–12/07
AT27LV256A
2. Pin Configurations
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Pin Name |
Function |
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A0 - A14 |
Addresses |
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O0 - O7 |
Outputs |
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Chip Enable |
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CE |
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Output Enable |
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OE |
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NC |
No Connect |
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2.128-lead SOIC Top View
VPP |
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1 |
28 |
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VCC |
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A12 |
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2 |
27 |
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A14 |
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A7 |
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3 |
26 |
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A13 |
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A6 |
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4 |
25 |
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A8 |
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A5 |
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5 |
24 |
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A9 |
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A4 |
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6 |
23 |
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A11 |
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A3 |
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7 |
22 |
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OE |
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A2 |
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8 |
21 |
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A10 |
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A1 |
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9 |
20 |
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CE |
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A0 |
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10 |
19 |
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O7 |
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O0 |
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11 |
18 |
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O6 |
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O1 |
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12 |
17 |
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O5 |
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O2 |
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13 |
16 |
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O4 |
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GND |
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14 |
15 |
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O3 |
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2.232-lead PLCC Top View
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A7 |
A12 |
VPP |
NC |
VCC |
A14 |
A13 |
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A6 |
4 |
3 |
2 |
1 |
32 |
31 |
30 |
A8 |
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5 |
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29 |
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A5 |
6 |
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28 |
A9 |
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A4 |
7 |
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27 |
A11 |
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A3 |
8 |
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26 |
NC |
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A2 |
9 |
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25 |
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OE |
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A1 |
10 |
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24 |
A10 |
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A0 |
11 |
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23 |
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CE |
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NC |
12 |
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22 |
O7 |
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O0 |
13 |
15 |
16 |
17 |
18 |
19 |
21 |
O6 |
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14 |
20 |
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O1 |
O2 |
GND |
NC |
O3 |
O4 |
O5 |
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2.328-lead TSOP (Type 1) Top View
OE |
22 |
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21 |
A10 |
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A11 |
23 |
20 |
CE |
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A9 |
24 |
19 |
O7 |
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A8 |
25 |
18 |
O6 |
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A13 |
26 |
17 |
O5 |
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A14 |
27 |
16 |
O4 |
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VCC |
28 |
15 |
O3 |
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VPP |
1 |
14 |
GND |
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A12 |
2 |
13 |
O2 |
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A7 |
3 |
12 |
O1 |
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A6 |
4 |
11 |
O0 |
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A5 |
5 |
10 |
A0 |
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A4 |
6 |
9 |
A1 |
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A3 |
7 |
8 |
A2 |
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Note: 1. PLCC Package Pins 1 and 17 are Don’t Connect.
2
0547G–EPROM–12/07
AT27LV256A
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.
4. Block Diagram
5. |
Absolute Maximum Ratings* |
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Temperature Under Bias |
.................................. -40°C to +85°C |
*NOTICE: Stresses beyond those listed under “Absolute |
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Maximum Ratings” may cause permanent dam- |
Storage Temperature ..................................... |
-65°C to +125°C |
age to the device. This is a stress rating only and |
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functional operation of the device at these or any |
Voltage on Any Pin with |
-2.0V to +7.0V(1) |
other conditions beyond those indicated in the |
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Respect to Ground ......................................... |
operational sections of this specification is not |
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Voltage on A9 with |
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implied. Exposure to absolute maximum rating |
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- 2.0V to +14.0V(1) |
conditions for extended periods may affect |
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Respect to Ground ...................................... |
device reliability |
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VPP Supply Voltage with |
- 2.0V to +14.0V(1) |
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Respect to Ground ....................................... |
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Note: |
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is |
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VCC + 0.75V DC which may be exceeded if certain precautions are observed (consult application notes) and which may |
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overshoot to +7.0V for pulses of less than 20 ns. |
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3
0547G–EPROM–12/07
6. Operating Modes
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Mode/Pin |
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CE |
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OE |
Ai |
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VPP |
VCC |
Outputs |
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Read(2) |
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VIL |
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VIL |
Ai |
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VCC |
VCC |
DOUT |
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Output Disable(2) |
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VIL |
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VIH |
X(1) |
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VCC |
VCC |
High Z |
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Standby(2) |
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VIH |
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X(1) |
X(1) |
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VCC |
VCC |
High Z |
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Rapid Program(3) |
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V |
IL |
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V |
IH |
Ai |
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V |
PP |
V |
CC |
D |
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IN |
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PGM Verify(3) |
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X(1) |
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VIL |
Ai |
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VPP |
VCC |
DOUT |
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Optional PGM Verify(3) |
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VIL |
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VIL |
Ai |
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VCC |
VCC |
DOUT |
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PGM Inhibit(3) |
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VIH |
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VIH |
X(1) |
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VPP |
VCC |
High Z |
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A9 = V |
(4) |
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Product Identification(3)(5) |
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H |
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V |
IL |
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V |
IL |
A0 = V or V |
V |
CC |
V |
CC |
Identification Code |
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IH |
IL |
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A1 - A14 = VIL |
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Notes: 1. X can be VIL or VIH.
2.Read, output disable, and standby modes require, 3.0V ≤VCC ≤3.6V, or 4.5V ≤VCC ≤5.5V.
3.Refer to Programming Characteristics. Programming modes require VCC = 6.5V.
4.VH = 12.0 ± 0.5V.
5.Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
7.DC and AC Operating Conditions for Read Operation
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AT27LV256A |
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-55 |
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-90 |
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Industrial Operating Temperature (Case) |
-40°C - 85°C |
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-40°C - 85°C |
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VCC Power Supply |
3.0V to 3.6V |
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3.0V to 3.6V |
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5V ± 10% |
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5V ± 10% |
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4 AT27LV256A 
0547G–EPROM–12/07
AT27LV256A
8. DC and Operating Characteristics for Read Operation
Symbol |
Parameter |
Condition |
Min |
Max |
Units |
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VCC = 3.0V to 3.6V |
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ILI |
Input Load Current |
VIN = 0V to VCC |
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±1 |
µA |
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ILO |
Output Leakage Current |
VOUT = 0V to VCC |
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±5 |
µA |
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IPP1(2) |
VPP(1) Read/Standby Current |
VPP = VCC |
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10 |
µA |
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ISB1 (CMOS), |
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= VCC ± 0.3V |
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20 |
µA |
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ISB |
VCC(1) Standby Current |
CE |
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ISB2 (TTL), CE = 2.0 to VCC + 0.5V |
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100 |
µA |
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ICC |
VCC Active Current |
f = 5 MHz, IOUT = 0 mA, |
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= VIL |
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8 |
mA |
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CE |
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VIL |
Input Low Voltage |
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-0.6 |
0.8 |
V |
VIH |
Input High Voltage |
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2.0 |
VCC + 0.5 |
V |
VOL |
Output Low Voltage |
IOL = 2.0 mA |
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0.4 |
V |
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VOH |
Output High Voltage |
IOH = -2.0 mA |
2.4 |
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V |
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VCC = 4.5V to 5.5V |
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ILI |
Input Load Current |
VIN = 0V to VCC |
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±1 |
µA |
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ILO |
Output Leakage Current |
VOUT = 0V to VCC |
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±5 |
µA |
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IPP1(2) |
VPP(1) Read/Standby Current |
VPP = VCC |
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10 |
µA |
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ISB1 (CMOS), |
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= VCC ± 0.3V |
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100 |
µA |
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ISB |
VCC(1) Standby Current |
CE |
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ISB2 (TTL), CE = 2.0 to VCC + 0.5V |
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1 |
mA |
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ICC |
VCC Active Current |
f = 5 MHz, IOUT = 0 mA, |
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= VIL |
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20 |
mA |
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CE |
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VIL |
Input Low Voltage |
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-0.6 |
0.8 |
V |
VIH |
Input High Voltage |
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2.0 |
VCC + 0.5 |
V |
VOL |
Output Low Voltage |
IOL = 2.1 mA |
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0.4 |
V |
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VOH |
Output High Voltage |
IOH = -400 µA |
2.4 |
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V |
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Notes: 1. VCC must be applied simultaneously with or before VPP, and removed simultaneously with or after VPP.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
5
0547G–EPROM–12/07
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