ATMEL AT27LV1026-55JI, AT27LV1026-55JC, AT27LV1026-45VI, AT27LV1026-45VC, AT27LV1026-45JI Datasheet

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Features

•

Fast Interleave Cycle Time - 35 ns

•

Continuous Memory Interleaving

– Unlimited Linear Access Data Output

•

Dual Voltage Range Operation

– Low Voltage Power Supply Range, 3.0V to 3.6V

or Standard 5V

•

Low Power CMOS Operation

– 108 mW max. Active at 25 MHz for VCC = 3.6V – 14.4 mW max. Standby fo r VCC = 3.6V

•

JEDEC Standard Surface Mount Packages

– 44-Lead PLCC – 40-Lead VSOP (10 x 14mm)

•

High Reliability CMOS Technology

– 2,000V ESD Protection – 200 mA Latchup Immunity

•

Rapid™ Programming Algorithm - 50

•

CMOS and TTL Compatible Inputs and Outputs

– JEDEC Standard for LVTTL

•

Integrated Product Identification Code

•

Commercial and Industrial Temperature Ranges

±±±±

10% Supply Range

µµµµ

s/word (typical)

1-Megabit (2 x 32K x 16) 16-Bit Interleaved Low-Voltage OTP EPROM

Description

The AT27LV1026 is a high performance 16-bit interleaved low-voltage 1,048,576-bit one-time programma ble read o nl y m emo ry ( OTP EPRO M) or ga ni ze d as 2 x 32K x 16 bits. It requires only one supply in the range of 3.0V to 3.6V i n normal read mode operation.

Pin Configurations

Pin Name Function

A0 - A15 Addresses O0 - O15 Outputs CS RD Read Strobe ALE Address Latch Enable PGM NC No Connect

Note: Both GND pins must be

O12 O11 O10

GND

O5 O4

Chip Select

Program Strobe

connected.

PLCC Top View VSOP Top View

O13

O15CSVPP

O14

654 7 8

10 11

15 16 17

181920212223242526

O3O2O1O0RD

VCC

ALE

GND

PGM

3144434241

GNDA0A1A2A3

A14

A15

A13 A12

A11

37 36

A10 A9

GND

A10 A8

A11

A12

A13

A14

A15

ALE

PGM

VCC

VPP

O15

O14

O13

O12

O11

O10

16 18

19 O7

Type 1

38 36 34 32

30 28 26 2417 22

27 25

O6 GND

AT27LV1026 Preliminary

GND A7 A5 A3

A1 RD O1 O3 O5

Rev. 0956D–02/98

This device is internally architected as two 32K x 16 memory banks, odd and even. To begin a non-linear access NLA cycle, (which typically equals a minimum of two linear access LA cycles), ALE is asserted high and CS

is asserted l ow. The tw o internal 15-bit co unters st ore the address for the odd and even banks and increment alternately during each sub se quent linear access LA cycl e. The LA cycle will be terminated when CS

is asserted high putting the device in standby m ode, or ano ther NLA cyc le starts. The LA cycle can be resumed when CS

is asserted low and ALE sta ys low. The A T27LV10 26 will co ntinuo usly output data within each LA cycle which is determined by the read RD

signal. Continuous interleave read operation is possible as there is no physical limit to the linear access LA output. When the last ad dress in the array i s reached the counters will wrap around to the first address location and continue.

For a NLA cycle where A 0 = 0 (ALE asserted high, CS asserted low), both even and odd counters wil l be loaded with new address (A1 - A15). Outputs (O0 - O15) from the even bank will be valid in t outputs from the odd bank will become valid in t

within the NLA cycle, the

ACCNLA

ACCLA

within the following LA cycle while the even counter increments by one to ready the data out for the next LA cycle. The outputs will have even or odd d ata alternating and the counters increment for the consecutive LA cycles until CS is asserted high putting the device in standby mode, or a new NLA cycle begins.

For a NLA cycle where A 0 = 1 (ALE asserted high, CS asserted low), the odd counter will be loaded with the new address (A1 - A15) while the even counter gets loaded with

the new address+1. Outputs (O0 - O15) from odd bank of memory will be valid in t

within the NLA cycle, the

ACCNLA

data output from the even bank of memory will become valid in t

within the following LA cycle while the odd

ACCLA

counter increments by one to ready the data out for the next LA cycle. The o utputs wil l have da ta from the o dd or even memory bank alternately and the counters increment for the following con se cutiv e L A c y cles un til CS

is asserted high putting the device in standby mode, or a new NLA cycle begins. Whe n coming out of stand by mode, the device can either enter into a new NLA cycl e or resume where the previous LA operation left off and was terminated by standby mode.

System Considerations

Switching under active conditions may produce transient voltage excursions. Unless accomm odated by the sy stem design, these transient s may exceed data sheet li mits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, l ow inherent inductance, ceramic capacitor should be utili zed for eac h dev ice. This capac itor should be connected between th e V nals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bul k electrolytic capacitor should be utilized, again connected between the V

and Ground ter minals. This c apacitor

should be positioned as close as possible to the point where the power supply is connected to the array.

and Ground termi -

Operating Table

If A0 = 0 at beginning of NLA cycle: If A0 = 1 at beginning of NLA cycle:

Consecutive Cycle

NLA Address Address from Even Bank NLA Address+1 Address from Odd Bank LA +1 - from Odd Bank LA - +1 from Even Bank LA - +1 from Even Bank LA +1 - from Odd Bank LA +1 - from Odd Bank LA - +1 from Even Bank LA - +1 from Even Bank LA +1 - from Odd Bank Standby HiZ Standby HiZ LA +1 - from Odd Band LA - +1 from Even Bank LA - +1 from Even Bank LA +1 - from Odd Band

Counter

Even Odd Even Odd

Outputs

Consecutive Cycle

and so on. and so on.

AT27LV1026

Counter

Outputs

Block Diagram

AT27LV1026

Address

Input

A-A

1 1 5

Odd Counter

32Kx16

ALE

Memory

Array

Logic

CLK_EVENCLK_ODD

Even Counter

32Kx16

Memory

Array

PGM

GND

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin with

Respect to Ground .........................................-2.0V to +7.0V

Voltage on A9 with

Respect to Ground .......................................-2.0V to +14.0V

VPP Supply Voltage with

Respect to Ground .......................................-2.0V to +14.0V

MUX

Data Outputs

O-O

0 1 5

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the dev ice . This is a s tress rating only an d functional oper ation of the de vi ce at these or any

(1)

other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating

(1)

conditions f or e xtended periods ma y af fect de vice reliability .

Note: 1. Minimum voltage is -0.6V DC which may under-

shoot to -2.0V for pulses of less than 20 ns. Max-

(1)

imum output pin v oltage is V

+ 0.75V DC which

may o versh oot to +7.0V f or pulse s of less than 20 ns.

Operating Modes

Mode/Pin ALE CS RD PGM A

(2)

(3)(5)

(2)

VIL/V

XVIHXVIHXXXV V V

VIL/V

XVIHXVIHXXV

XVILXVIHVIL/V

Non-Linear Acce ss Cycle Linear Access Cycle Standby Rapid Program PGM Verify PGM Inhibit

(2)

(3)

Product Identification

(1)

A1 - A

Ai X V XXV

Ai V Ai V

A9 = VH

A1 - A15 = V

Notes: 1. X can be VIL or VIH.

2. Non-Linear and Linear Access Cycles, and standby modes require, 3.0V ≤ V

3. Refer to Programming Characteristics. Programming modes require VCC = 6.5V.

4. VH = 12.0 ± 0.5V.

5. Two identifier words may be selected. All Ai inputs are held low (V ) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word.

low (V

), except A9 which is set to VH and A0 which is toggled

DC and AC Operating Conditions for Read Operation

AT27LV1026

-35 -45 -55

(4)

≤ 3.6V, or 4.5V ≤ VCC ≤ 5.5V.

(2)

(3)

Outputs

OUT

High Z

OUT

High Z

Identific ation Code

Operating Temperature (Case)

Power Supply

Com. 0°C - 70°C0°C - 70°C0°C - 70°C Ind. -40°C - 85°C-40°C - 85°C-40°C - 85°C

3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 5V ± 10% 5V ± 10% 5V ± 10%

AT27LV1026

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