The AT27LV040A is a high performance, low power, low voltage, 4,194,304 bit onetime programmable read only memory (OTP EPROM) organized as 512K by 8 bits.
It requires only one supply in the range of 3.0 to 3.6V in normal read mode operation,
making it ideal for fast, portable systems using battery power.
Atmel’s innovative design techniques provide fast speeds that rival 5V parts while
keeping the low power consumption of a 3V supply. At V
accessed in less than 120 ns. With a typical power dissipation of only 18 mW at 5
MHz and V
standard 5V EPROM. Standby mode supply current is typically less than 1 µA at
3.3V.
= 3.3V, the AT27LV040A consumes less than one half the power of a
The AT27LV040A is available in industry standard
JEDEC-approved one-time programmable (OTP) plastic
PLCC and TSOP packages. All devices feature two-line
control (
bus contention.
The AT27LV040A operating with V
TTL level outputs that are compatible with standard TTL
logic devices operating at V
capable of standard 5-volt operation making it ideally
suited for dual supply range systems or card products that
are pluggable in both 3-volt and 5-volt hosts.
Atmel’s AT27LV040A has additional features to ensure
high quality and efficient production use. The Rapid
gramming Algorithm reduces the time required to program
the part and guarantees reliable programming. Programming time i s typically only 100 µs/byte. The Integrated
Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry
standard programming equipment to select the proper
programming algorithms and voltages. The AT27LV040A
programs exactly the same way as a standard 5V
AT27C040 and uses the same programming equipment.
CE, OE) to give designers the flexibility to prevent
at 3.0V produces
CC
= 5.0V. The device is also
CC
Pro-
System Considerations
Switching between active and standby conditions via the
Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these
transients may exceed data sheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor
should be utilized for each device. This capacitor should
be connected between the V
the device, as close to the device as possible. Additionally,
to stabilize the supply voltage level on printed circuit
boards with large EPROM arrays, a 4.7 µF bulk electrolytic
capacitor should be utilized, again connected between the
and Ground terminals. This capacitor should be posi-
V
CC
tioned as close as possible to the point where the power
supply is connected to the array.
and Ground terminals of
CC
3-116AT27LV040A
AT27LV040A
Block Diagram
Absolute Maximum Ra ti ngs *
Temperature Under Bias .................. -40°C to +85°C
Storage Temperature...................... -65°C to +125°C
Voltage on Any Pin with
Respect to Ground.........................-2.0V to +7.0V
Voltage on A9 with
Respect to Ground ......................-2.0V to +14.0V
VPP Supply Voltage with
Respect to Ground.......................-2.0V to +14.0V
*NOTICE: Stresses beyond those listed unde r “Absolu te Maxi-
mum Ratings” may cause permanent da ma ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note: 1. Minimum voltage is -0.6V dc which may undershoot
to -2.0V for pulses of less than 20 ns. Maximum
output pin voltage is V
be exceeded if certain precautions are observed
(consult application notes) and which may overshoot to +7.0 volts for pulses of less than 20 ns.
+ 0.75V dc which may
CC
(1)
(1)
(1)
Operating Modes
Mode \ Pin
(2)
Read
Output Disable
Standby
(2)
Rapid Program
PGM Verify
PGM Inhibit
Product Identification
Notes: 1. X can be VIL or VIH.
2. Read, output disable, and standby modes
require, 3.0V ≤ VCC ≤ 3.6V, or 4.5V ≤ VCC ≤ 5.5V.
3. Refer to Pro gra mmin g Cha racte ris tics . Prog ramming
modes require VCC = 6.5V.
(2)
(3)
(3)
(3)
(3, 5)
CEOEAiV
V
IL
XV
V
IH
V
IL
V
IL
IH
Ai X
XXV
XXXV
V
IH
AiV
XVILAiV
V
IH
V
IL
V
IH
V
IL
A0 = VIH or VIL
XVPPVCC
A9 = VH
A1 - A18 = V
(4)
IL
4. VH = 12.0 ± 0.5V.
5. Two identifier bytes may be selected. Al l Ai in puts are held
low (VIL), except A9 which is set to VH and A0 which is toggled low (V
and high (V
) to select the Manuf ac tu rer’s Identifi ca ti on byte
IL
) to select the Dev ice Code byte.
IH
PP
(1)
PP
PP
XV
V
CC
VCC
CC
CC
VCC
VCC
CC
(2)
(2)
(2)
(3)
(3)
(3)
(3)
Outputs
D
OUT
High Z
High Z
D
IN
D
OUT
High Z
Identification
Code
3-117
DC and AC Operating Conditions f or Read Operation
Input Rise and Fall Times (10% to 90%).....................20 ns
Input Pulse Leve ls.......... .. .......... .. .......... .. ......0.45 V to 2. 4V
Input Timing Reference Level... .. .......... .. .. .......0.8 V to 2. 0V
Output Timing Ref erence Level............. .. ........0. 8V to 2.0 V
Test
Conditions*
(2)
(2)
(3)
(1)
Limits
MinMax
0130ns
95105µs
150ns
50ns
Units
Rapid Programming Algor ithm
A 100 µs CE pulse width is used to program. The address
is set to the first location. V
raised to 13.0V. Each address is first programmed with
one 100 µs
CE pulse without verification. Then a verification/reprogramming loop is executed for each address. In
the event a byte fails to pass verification, up to 10 successive 100 µs pulses are applied with a verification after
each pulse. If the byte fails to verify after 10 pulses have
been applied, the part is considered failed. After the byte
verifies properly, the next address is selected until all have
been checked. V
is then lowered to 5.0V and VCC to
PP
5.0V. All bytes are read again and compar ed with the
original data to determine if the device passes or fails.
is raised to 6.5V and VPP is
CC
Notes: 1. V
Atmel’s 27LV040 A Inte grated
must be applied simultaneou sl y or before
CC
and removed simultane ou sl y or af te r VPP.
V
PP
2. This parameter is only sampl ed and is not 100%
tested. Output Float is defined as the point where
data is no longer driven —see timing diagram.
3. Program Pulse width tolerance is 100 µsec ± 5%.
(1)
Product Identification Code
Pins
Codes
Manufacturer0000111101E
Device Type 1000010110B
Note:1. The AT27LV040A has the same Product
A0 O7 O6 O5 O4 O3 O2 O1 O0
Identification Code as the AT27C040. Both are
programming compatible.
Hex
Data
3-122AT27LV040A
AT27LV040A
Ordering Information
(mA)
I
t
ACC
(ns)
12080.02AT27LV040A-12JC32JCommercial
15080.02AT27LV040A-15JC32JCommercial
CC
V
= 3.6V
CC
ActiveStandby
80.02AT27LV040A-12JI32JIndustrial
80.02AT27LV040A-15JI32JIndustrial
Ordering CodePackageOperation Range
AT27LV040A-12TC32T(0°C to 70°C)
AT27LV040A-12TI32T(-40°C to 85°C)
AT27LV040A-15TC32T(0°C to 70°C)
AT27LV040A-15TI32T(-40°C to 85°C)
= Preliminary Informat ion
Package Type
32J32 Lead, Plastic J-Leade d Chip Carrier (PLCC)
32T32 Lead, Plasti c Thin Small Out line Package (TSOP)
3-123
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