ATMEL AT27LV040A User Manual

BDTIC www.BDTIC.com/ATMEL

Features

• Fast Read Access Time – 90 ns

• Dual Voltage Range Operation

– Low Voltage Power Supply Range, 3.0V to 3.6V

or Standard 5V ± 10% Supply Range

• Compatible With JEDEC Standard AT27C040

• Low Power 3.3-volt CMOS Operation

– 20 µA Max (Less than 1 µA Typical) Standby for V
– 36 mW Max Active at 5 MHz for V

• JEDEC Standard Packages

– 32-lead PLCC
– 32-lead TSOP
– 32-lead VSOP

• High Reliability CMOS Technology

– 2,000V ESD Protection
– 200 mA Latchup Immunity

• Rapid Programming Algorithm – 100 µs/Byte (Typical)

• CMOS and TTL Compatible Inputs and Outputs

– JEDEC Standard for LVTTL

• Integrated Product Identification Code

• Industrial Temperature Range

• Green (Pb/Halide-free) Packaging Option

= 3.6V

CC

= 3.6V

CC

4-Megabit
(512K x 8)
Low Voltage
OTP EPROM

AT27LV040A

1. Description

The AT27LV040A is a high-performance, low-power, low-voltage, 4,194,304-bit one­time programmable read-only memory (OTP EPROM) organized as 512K by 8 bits. It
requires only one supply in the range of 3.0 to 3.6V in normal read mode operation,
making it ideal for fast, portable systems using battery power.

Atmel’s innovative design techniques provide fast speeds that rival 5V parts while
keeping the low power consumption of a 3V supply. At V
accessed in less than 90 ns. With a typical power dissipation of only 18 mW at 5 MHz
and V
dard 5V EPROM. Standby mode supply current is typically less than 1 µA at 3.3V.

The AT27LV040A is available in industry-standard JEDEC-approved one-time pro­grammable (OTP) plastic PLCC, TSOP, and VSOP packages. All devices feature two­line control (CE

The AT27LV040A operating with V
compatible with standard TTL logic devices operating at V
also capable of standard 5-volt operation making it ideally suited for dual supply range
systems or card products that are pluggable in both 3-volt and 5-volt hosts.

Atmel’s AT27LV040A has additional features to ensure high quality and efficient pro­duction use. The Rapid Programming Algorithm reduces the time required to program
the part and guarantees reliable programming. Programming time is typically only
100 µs/byte. The Integrated Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry-standard programming
equipment to select the proper programming algorithms and voltages. The
AT27LV040A programs exactly the same way as a standard 5V AT27C040 and uses
the same programming equipment.

= 3.3V, the AT27LV040A consumes less than one half the power of a stan-

CC

, OE) to give designers the flexibility to prevent bus contention.

at 3.0V produces TTL level outputs that are

CC

= 3.0V, any byte can be

CC

= 5.0V. The device is

CC

0557D–EPROM–12/07

2. Pin Configurations

Pin Name Function

A0 - A18 Addresses

O0 - O7 Outputs

CE

OE

2.1 32-lead TSOP/VSOP (Type 1) Top View

A11

A9

A8
A13
A14
A17
A18

VCC

VPP

A16
A15
A12

A7

A6

A5

A4

2.2 32-lead PLCC Top View

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Chip Enable

Output Enable

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

OE
A10
CE
O7
O6
O5
O4
O3
GND
02
01
O0
A0
A1
A2
A3

A12

A15

A16

VPP

VCC

A18

A17

432

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

O0

2

AT27LV040A

14151617181920

O1

O2

1

O3O4O5

GND

323130

29
28
27
26
25
24
23
22
21

O6

A14
A13
A8
A9
A11
OE
A10
CE
O7

0557D–EPROM–12/07

3. System Considerations

Switching between active and standby conditions via the Chip Enable pin may produce transient
voltage excursions. Unless accommodated by the system design, these transients may exceed
datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency,
low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor
should be connected between the V
device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards
with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again con­nected between the V
possible to the point where the power supply is connected to the array.

4. Block Diagram

AT27LV040A

and Ground terminals of the device, as close to the

CC

and Ground terminals. This capacitor should be positioned as close as

CC

5. Absolute Maximum Ratings*

Temperature Under Bias.................................. -40°C to +85°C

Storage Temperature ..................................... -65°C to +125°C

Voltage on Any Pin with

Respect to Ground .........................................-2.0V to +7.0V

Voltage on A9 with

Respect to Ground ......................................-2.0V to +14.0V

VPP Supply Voltage with

Respect to Ground .......................................-2.0V to +14.0V

Note: 1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is

V

+ 0.75V DC which may be exceeded if certain precautions are observed (consult application notes) and which may

CC

overshoot to +7.0V for pulses of less than 20 ns.

(1)

(1)

(1)

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability

0557D–EPROM–12/07

3

6. Operating Modes

Mode/Pin CE OE Ai V

(2)

Read

Output Disable

Standby

Rapid Program

PGM Verify

PGM Inhibit

(2)

(2)

(3)

(3)

(3)

Product Identification

(3)(5)

V

IL

V

IL

Ai X

XVIHXXVCCHigh Z

V

IH

V

IL

XXXVCCHigh Z

V

IH

Ai V

XVILAi V

V

IH

V

IL

V

IH

V

IL

XVPPV

A9 = V

(4)

H

A0 = VIH or VIL
A1 - A18 = V

IL

PP

(1)

PP

PP

XVCCIdentification Code

Notes: 1. X can be VIL or VIH.

2. Read, output disable, and standby modes require, 3.0V ≤ V

3. Refer to Programming Characteristics. Programming modes require V

≤ 3.6V, or 4.5V ≤ VCC ≤ 5.5V.

CC

= 6.5V.

CC

4. VH = 12.0 ± 0.5V.

5. Two identifier bytes may be selected. All Ai inputs are held low (V

), except A9 which is set to VH and A0 which is toggled

IL

low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.

7. DC and AC Operating Conditions for Read Operation

AT27LV040A-90

Industrial Operating Temperature (Case) -40°C - 85°C

V

CC

V

CC

V

CC

V

CC

CC

Outputs

D

OUT

D

IN

D

OUT

High Z

VCC Power Supply

3.0V to 3.6V

5V ± 10%

4

AT27LV040A

0557D–EPROM–12/07

AT27LV040A

8. DC and Operating Characteristics for Read Operation

Symbol Parameter Condition Min Max Units

= 3.0V to 3.6V

V

CC

I

LI

I

LO

(2)

I

PP1

I

SB

I

CC

V

IL

V

IH

V

OL

V

OH

= 4.5V to 5.5V

V

CC

I

LI

I

LO

(2)

I

PP1

I

SB

I

CC

V

IL

V

IH

V

OL

V

OH

Notes: 1. VCC must be applied simultaneously with or before VPP, and removed simultaneously with or after VPP.

Input Load Current VIN = 0V to V

Output Leakage Current V

(1)

V

Read/Standby Current VPP = V

PP

(1)

V

Standby Current

CC

= 0V to V

OUT

CC

I

(CMOS), CE = V

SB1

(TTL), CE = 2.0 to VCC + 0.5V 100 µA

I

SB2

VCC Active Current f = 5 MHz, I

CC

CC

CC ±

= 0 mA, CE = V

OUT

0.3V 20 µA

IL

±1µA

±5µA

10 µA

10 mA

Input Low Voltage -0.6 0.8 V

Input High Voltage 2.0 VCC + 0.5 V

Output Low Voltage IOL = 2.0 mA 0.4 V

Output High Voltage IOH = -2.0 mA 2.4 V

Input Load Current VIN = 0V to V

Output Leakage Current V

(1)

V

Read/Standby Current VPP = V

PP

(1)

V

Standby Current

CC

= 0V to V

OUT

CC

I

(CMOS), CE = VCC ± 0.3V 100 µA

SB1

(TTL), CE = 2.0 to VCC + 0.5V 1 mA

I

SB2

VCC Active Current f = 5 MHz, I

CC

CC

= 0 mA, CE = V

OUT

IL

±1µA

±5µA

10 µA

30 mA

Input Low Voltage -0.6 0.8 V

Input High Voltage 2.0 VCC + 0.5 V

Output Low Voltage IOL = 2.1 mA 0.4 V

Output High Voltage IOH = -400 µA 2.4 V

2. V

may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.

PP

0557D–EPROM–12/07

5

9. AC Characteristics for Read Operation

VCC = 3.0V to 3.6V and 4.5V to 5.5V

Symbol Parameter Condition

(3)

t

t

t

t

ACC

CE

OE

DF

(2)

(2)(3)

(4)(5)

Address to Output Delay CE = OE = V

CE to Output Delay OE = V

OE to Output Delay CE = V

OE or CE High to Output Float, Whichever
Occurred First

AT27LV040A-90

UnitsMin Max

IL

IL

IL

90 ns

90 ns

50 ns

60 ns

t

OH

10. AC Waveforms for Read Operation

Output Hold from Address, CE or OE,
Whichever Occurred First

0ns

(1)

Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V. See Input Test Waveforms

and Measurement Levels.

2. OE

may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.

3. OE may be delayed up to t

- tOE after the address is valid without impact on t

ACC

ACC

.

4. This parameter is only sampled and is not 100% tested.

5. Output float is defined as the point when data is no longer driven.

6

AT27LV040A

0557D–EPROM–12/07

11. Input Test Waveforms and Measurement Level

, tF < 20 ns (10% to 90%)

t

R

12. Output Test Load

AT27LV040A

Note: CL = 100 pF including
jig capacitance.

13. Pin Capacitance

f = 1 MHz, T = 25°C

Symbol Typ Max Units Conditions

C

IN

C

OUT

Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

(1)

48pFV

812pFV

IN

OUT

= 0V

= 0V

0557D–EPROM–12/07

7

14. Programming Waveforms

(1)

Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.

2. t

and t

OE

3. When programming the AT27LV040A a 0.1 µF capacitor is required across V
transients.

are characteristics of the device but must be accommodated by the programmer.

DFP

and ground to suppress spurious voltage

PP

8

AT27LV040A

0557D–EPROM–12/07

15. DC Programming Characteristics

TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V

Symbol Parameter Test Conditions

AT27LV040A

Limits

UnitsMin Max

I

V

V

V

V

I

I

V

LI

IL

IH

OL

OH

CC2

PP2

ID

Input Load Current VIN=VIL,V

IH

Input Low Level -0.6 0.8 V

Input High Level 2.0 VCC + 0.5 V

Output Low Voltage IOL = 2.1 mA 0.4 V

Output High Voltage IOH = -400 µA 2.4 V

VCC Supply Current (Program and Verify) 40 mA

VPP Supply Current CE = V

IL

A9 Product Identification Voltage 11.5 12.5 V

16. AC Programming Characteristics

TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V

Limits

Symbol Parameter Test Conditions

t

AS

t

OES

t

DS

t

AH

t

DH

t

DFP

t

VPS

t

VCS

t

PW

t

OE

t

PRT

Address Setup Time

OE Setup Time 2 µs

Input Rise and Fall Times:

Data Setup Time 2 µs

Address Hold Time 0 µs

Data Hold Time 2 µs

OE High to Output Float Delay

(2)

VPP Setup Time 2 µs

Input Pulse Levels:

Input Timing Reference Level:

VCC Setup Time 2 µs

CE Program Pulse Width

Data Valid from OE

(3)

(2)

Output Timing Reference Level:

VPP Pulse Rise Time During
Programming

Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven –
see timing diagram.

3. Program Pulse width tolerance is 100 µsec ± 5%.

(1)

(10% to 90%) 20 ns

.0.45V to 2.4V

0.8V to 2.0V

0.8V to 2.0V

2µs

0130ns

95 105 µs

50 ns

17. Atmel’s AT27LV040A Integrated Product Identification Code

±10 µA

20 mA

UnitsMin Max

150 ns

(1)

Pins

Codes

Hex

DataA0 O7 O6 O5 O4 O3 O2 O1 O0

Manufacturer 000011110 1E

Device Type 100001011 0B

Note: 1. The AT27LV040A has the same Product Identification Code as the AT27C040. Both are programming compatible.

9

0557D–EPROM–12/07

18. Rapid Programming Algorithm

A 100 µs CE pulse width is used to program. The address is set to the first location. VCC is raised
to 6.5V and V
without verification. Then a verification/reprogramming loop is executed for each address. In the
event a byte fails to pass verification, up to 10 successive 100
fication after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is
considered failed. After the byte verifies properly, the next address is selected until all have been
checked. V
with the original data to determine if the device passes or fails.

is raised to 13.0V. Each address is first programmed with one 100 µs CE pulse

PP

is then lowered to 5.0V and VCC to 5.0V. All bytes are read again and compared

PP

µs pulses are applied with a veri-

10

AT27LV040A

0557D–EPROM–12/07

19. Ordering Information

19.1 Standard Package

(mA)

I

CC

= 3.6V

t

ACC

(ns)

90 8 0.02 AT27LV040A-90JI

V

CC

Ordering Code Package Operation RangeActive Standby

AT27LV040A-90TI
AT27LV040A-90VI

32J
32T
32V

AT27LV040A

Industrial

(-40°C to 85°C)

(1)

Note:

Not recommended for new designs. Use Green package option.

19.2 Green Package Option (Pb/Halide-free)

I

(mA)

CC

t

ACC

(ns)

90 8 0.02 AT27LV040A-90JU

Note: 1. The 32-lead VSOP package is not recommended for new designs.

VCC = 3.6V

Ordering Code Package Operation RangeActive Standby

AT27LV040A-90TU

32J
32T

Industrial

(-40°C to 85°C)

32J

32T

32V

0557D–EPROM–12/07

Package Type

32-lead, Plastic J-leaded Chip Carrier (PLCC)

32-lead, Plastic Thin Small Outline Package (TSOP)

32-lead, Plastic Thin Small Outline Package (VSOP)

11

20. Packaging Information

20.1 32J – PLCC

1.14(0.045) X 45˚

B

e

0.51(0.020)MAX

45˚ MAX (3X)

Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.

2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.

3. Lead coplanarity is 0.004" (0.102 mm) maximum.

PIN NO. 1
IDENTIFIER

D1

D

D2

1.14(0.045) X 45˚

E1 E

0.318(0.0125)

0.191(0.0075)

E2

B1

A2

A1

A

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A 3.175 – 3.556

A1 1.524 – 2.413

A2 0.381 – –

D 12.319 – 12.573

D1 11.354 – 11.506 Note 2

D2 9.906 – 10.922

E 14.859 – 15.113

E1 13.894 – 14.046 Note 2

E2 12.471 – 13.487

B 0.660 – 0.813

B1 0.330 – 0.533

e 1.270 TYP

MIN

NOM

MAX

NOTE

10/04/01

12

2325 Orchard Parkway

R

San Jose, CA 95131

AT27LV040A

TITLE

32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)

DRAWING NO.

32J

0557D–EPROM–12/07

REV.

B

20.2 32T – TSOP

AT27LV040A

PIN 1

Pin 1 Identifier

D1

D

e

E

b

A2

A

SEATING PLANE

A1

Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.

2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

0º ~ 8º

L

SYMBOL

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 19.80 20.00 20.20

D1 18.30 18.40 18.50 Note 2

E 7.90 8.00 8.10 Note 2

L 0.50 0.60 0.70

L1 0.25 BASIC

b 0.17 0.22 0.27

c 0.10 – 0.21

e 0.50 BASIC

c

L1

GAGE PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

NOM

MAX

NOTE

2325 Orchard Parkway

R

San Jose, CA 95131

0557D–EPROM–12/07

TITLE

32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline

Package, Type I (TSOP)

DRAWING NO.

32T

10/18/01

REV.

B

13

20.3 32V – VSOP

PIN 1

Pin 1 Identifier

D1

D

e

E

b

A2

A

SEATING PLANE

A1

Notes: 1. This package conforms to JEDEC reference MO-142, Variation BA.

2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

0º ~ 8º

L

SYMBOL

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 13.80 14.00 14.20

D1 12.30 12.40 12.50 Note 2

E 7.90 8.00 8.10 Note 2

L 0.50 0.60 0.70

L1 0.25 BASIC

b 0.17 0.22 0.27

c 0.10 – 0.21

e 0.50 BASIC

c

L1

GAGE PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

NOM

MAX

NOTE

14

2325 Orchard Parkway

R

San Jose, CA 95131

AT27LV040A

TITLE

32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline

Package, Type I (VSOP)

DRAWING NO.

32V

0557D–EPROM–12/07

10/18/01

REV.

B