ATMEL AT27C520-90XI, AT27C520-90XC, AT27C520-90TI, AT27C520-90TC, AT27C520-90SI Datasheet

Features

•

8-Bit Multiplexed Addresses/Outputs

•

Fast Read Access Time - 70 ns

•

Low Power CMOS Operation

– 20 mA max. Active at 5 MHz

•

20-Lead TSSOP Package

•

20-Lead SOIC Package

•

28-Lead TSOP Package

•

5V ± 10% Supply

•

High Reliability CMOS Technology

– 2,000V ESD Protection
– 200 mA Latchup Immunity

•

Rapid™ Programming Algorithm - 50

•

CMOS and TTL Compatible Inputs and Outputs

•

Integrated Product Identification Code

•

Commercial and Industrial Temperature Range

µµµµ

s/byte (typical)

512K (64K x 8)
Multiplexed
Addresses/

Description

The AT27C520 is a low-power, high performance 524,288 bit one-time programmable
read only memory ( OTP EP ROM) o rgani zed 6 4K by 8 bits . It i ncorpor ates la tches for
the 8 lower order address bits to mul ti ple x with the 8 dat a bits . Thi s minim iz es sy st em
chip count, reduces cost, and simplifies the design of multi plexed bus syst ems. It
requires only one 5V power supply in normal read mode operation. Any byte can be
accessed in le ss th an 70 n s, el imina ting th e need for s peed r educi ng WA IT state s on
high performance microprocessor systems.

Atmel’s scaled CMO S tec hnol ogy prov ides high speed, lower active powe r cons ump­tion, and significantly faster programming. Power consumption is typically only 8 mA
in Active Mode.

The AT27C520 is avail able in 173 m il, 20-pin TSSO P; 300 m il, 20-p in S OIC; an d 28­pin TSOP, one-time programmable (OTP) plastic packages.

(continued)

Pin Configurations

Pin Name Function

A8 - A15 Addresses
AD0 - AD7 Addresses/Outputs
OE

/V

PP

ALE Address Latch Enable

Output Enable/V

PP

TSSOP Top View

1

A10

2

A12

3

A14

4

ALE

5

VCC

A15
A13
A11

6
7
8
9
10

A9

OE/VPP

20

A8

19

AD1

18

AD3

17

AD5

16

AD7

15

GND

14

AD6

13

AD4

12

AD2

11

AD0

Outputs
OTP EPROM

AT27C520

A10

A12
A14
ALE

VCC

OE/VPP

A15
A13
A11

TSOP Top View

22
23

NC

24

NC

25
26
27

28

1
2
3
4
5

NC

6

NC

7

A9

21

A8

20

NC

19

NC

18

AD1

17

AD3

16

AD5

15

AD7

14

GND

13

AD6

12

AD4

11

AD2

10

NC

9

NC

8

AD0

SOIC Top View

OE/VPP

A15
A13
A11

A9
AD0
AD2
AD4
AD6

GND

1

20
2
3
4
5
6
7
8
9
10

VCC

19

ALE

18

A14

17

A12

16

A10

15

A8

14

AD1

13

AD3

12

AD5

11

AD7

Rev. 0752C-C–01/98

1

With 64K byte storage capability, the AT27C520 allows
firmware to be stored reliably and to be accessed by the
system without the delays of mass storage media.

Atmel's 27C520 ha s additional features to ensure high
quality and efficient production use. The Rapid

™

Program­ming Algorithm reduces the time required to program the
part and guarantees reliable programming. Programming
time is typically onl y 50 µs/byte. Th e Integrated P roduct
Identification Code electronic ally identi fies the devic e and
manufacturer. This feature is used by industry standard
programmin g equip ment to se lect th e prope r prog rammi ng
algorithms and voltages.

Block Diagram

V

CC

GND

System Considerations

Switching under active conditions may produce transient
voltage excursions. Unless accomm odated by the sy stem
design, these transient s may exceed data sheet li mits,
resulting in device non-conformance. At a minimum, a 0.1
µF high frequency, low inherent inductance, ceramic
capacitor should be utili zed for eac h dev ice. This capac itor
should be connected between th e V
nals of the device, as close to the device as possible. Addi­tionally, to stabilize the supply voltage level on printed cir­cuit boards with larg e EPROM array s, a 4.7 µF bulk elec­trolytic capacitor should be utilized, again connected
between the V

and Ground ter minals. This c apacitor

CC

should be positioned as close as possible to the point
where the power supply is connected to the array.

8

and Ground termi -

CC

OE/VPP

ALE

AD7 - AD0

A15 - A8

OE, ALE, AND

PROGRAM LOGIC

Y DECODER

LATCHES

8

X DECODER

OUTPUT

BUFFERS

Y-GATING

CELL MATRIX

IDENTIFICATION

2

AT27C520

Absolute Maximum Ratings*

AT27C520

Temperature Under Bias................................-55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin with

Respect to Ground .........................................-2.0V to +7.0V

Voltage on A9 with

Respect to Ground ......................................-2.0V to +14.0V

(1)

(1)

Note: 1. Minimum voltage is -0.6V DC which may under-

VPP Supply Voltage with

Respect to Ground .......................................-2.0V to +14.0V

(1)

Operating Modes

Mode/Pin ALE OE/V

Read V
Output Disable VIL/V
Address Latch Enable V
Rapid Program

Product Identification

Notes: 1. X can be VIL or V

2. Refer to Programming Characteristics.

3. VH = 12.0 ± 0.5V.

4. Two identifier bytes may be selected. All A8 - A15 inputs are held low (V

(2)

toggled low (V

(3)

IH.

) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.

IL

IL

IH

IH

V

IH

V

IL

Maximum Ratings” may cause permanent dam­age to the dev ice . This is a stress ra ting onl y and
functional oper ati on of the device at thes e or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or exten ded periods may af fect de vice
reliability.

shoot to -2.0V f or pul ses o f less than 20 ns . M ax­imum output pin voltage is V

+ 0.75V DC

CC

which may overshoot to +7.0V for pulses of less
than 20 ns.

PP

V

IL

V

IH

V

IH

V

PP

V

IL

A8 - A15 AD0 - AD7

Ai D

(1)

X

OUT

High Z/A0 - A7

XA0 - A7

Ai D

A9 = V

A8 = VIH or V

A10 - A15 = V

), except A9 which is set to VH and A8 which is

IL

(4)

H

IL

IL

Identification Code

IN

3