ATMEL AT27C1024 User Manual
BDTIC www.BDTIC.com/ATMEL
Features
•Fast Read Access Time – 45 ns
•Low-Power CMOS Operation
–100 µA Max Standby
–30 mA Max Active at 5 MHz
•JEDEC Standard Packages
–40-lead PDIP
–44-lead PLCC
–40-lead VSOP
•Direct Upgrade from 512K (AT27C516) EPROM
•5V ± 10% Power Supply
•High-Reliability CMOS Technology
–2000V ESD Protection
–200 mA Latchup Immunity
•Rapid Programming Algorithm – 100 µs/Word (Typical)
•CMOS and TTL Compatible Inputs and Outputs
•Integrated Product Identification Code
•Industrial and Automotive Temperature Ranges
•Green (Pb/Halide-free) Packaging Option
1. Description
The AT27C1024 is a low-power, high-performance 1,048,576 bit one-time programmable read-only memory (OTP EPROM) organized 64K by 16 bits. It requires only one 5V power supply in normal read mode operation. Any word can be accessed in less than 45 ns, eliminating the need for speed reducing WAIT states. The by-16 organization make this part ideal for high-performance 16and 32-bit microprocessor systems.
In read mode, the AT27C1024 typically consumes 15 mA. Standby mode supply current is typically less than 10 µA.
The AT27C1024 is available in industry-standard JEDEC-approved one-time programmable (OTP) plastic PDIP, PLCC, and VSOP packages. The device features two-line control (CE, OE) to eliminate bus contention in high-speed systems.
With high density 64K word storage capability, the AT27C1024 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media.
Atmel’s AT27C1024 have additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/word. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages.
1-Megabit
(64K x 16) OTP EPROM
AT27C1024
0019M–EPROM–12/07
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Pin Configurations |
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Pin Name |
Function |
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A0 - A15 |
Addresses |
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O0 - O15 |
Outputs |
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Chip Enable |
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CE |
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Output Enable |
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OE |
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Program Strobe |
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PGM |
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NC |
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No Connect |
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Note: |
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Both GND pins must be connected. |
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2.140-lead PDIP Top View
VPP |
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1 |
40 |
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VCC |
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2 |
39 |
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CE |
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PGM |
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O15 |
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3 |
38 |
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NC |
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O14 |
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4 |
37 |
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A15 |
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O13 |
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5 |
36 |
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A14 |
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O12 |
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6 |
35 |
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A13 |
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O11 |
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7 |
34 |
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A12 |
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O10 |
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33 |
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A11 |
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O9 |
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9 |
32 |
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A10 |
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O8 |
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10 |
31 |
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A9 |
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GND |
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11 |
30 |
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GND |
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O7 |
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12 |
29 |
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A8 |
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O6 |
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28 |
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A7 |
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O5 |
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14 |
27 |
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A6 |
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O4 |
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15 |
26 |
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A5 |
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O3 |
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16 |
25 |
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A4 |
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O2 |
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17 |
24 |
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A3 |
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O1 |
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18 |
23 |
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A2 |
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O0 |
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19 |
22 |
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A1 |
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OE |
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20 |
21 |
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A0 |
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2.240-lead VSOP Top View – Type 1
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GND |
A9 |
1 |
40 |
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A10 |
2 |
39 |
A8 |
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A11 |
3 |
38 |
A7 |
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A12 |
4 |
37 |
A6 |
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A13 |
5 |
36 |
A5 |
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A14 |
6 |
35 |
A4 |
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A15 |
7 |
34 |
A3 |
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NC |
8 |
33 |
A2 |
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PGM |
9 |
32 |
A1 |
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VCC |
10 |
31 |
A0 |
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VPP |
11 |
30 |
OE |
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CE |
12 |
29 |
O0 |
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O15 |
13 |
28 |
O1 |
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O14 |
14 |
27 |
A2 |
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O13 |
15 |
26 |
O3 |
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O12 |
16 |
25 |
O4 |
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O11 |
17 |
24 |
O5 |
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O10 |
18 |
23 |
O6 |
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O9 |
19 |
22 |
O7 |
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O8 |
20 |
21 |
GND |
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2.344-lead PLCC Top View
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O13 |
O14 |
O15 |
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CE |
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VPP |
NC |
VCC |
PGM |
NC |
A15 |
A14 |
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O12 |
6 |
5 |
4 |
3 |
2 |
1 |
44 |
43 |
42 |
41 |
40 |
A13 |
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7 |
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39 |
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O11 |
8 |
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38 |
A12 |
O10 |
9 |
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37 |
A11 |
O9 |
10 |
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36 |
A10 |
O8 |
11 |
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35 |
A9 |
GND |
12 |
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34 |
GND |
NC |
13 |
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33 |
NC |
O7 |
14 |
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32 |
A8 |
O6 |
15 |
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31 |
A7 |
O5 |
16 |
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30 |
A6 |
O4 |
17 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
29 |
A5 |
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18 |
28 |
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O3 |
O2 |
O1 |
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O0 |
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OE |
NC |
A0 |
A1 |
A2 |
A3 |
A4 |
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2 AT27C1024
0019M–EPROM–12/07
AT27C1024
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.
4. Block Diagram
5. |
Absolute Maximum Ratings* |
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Temperature Under Bias.............................. |
-55° C to + 125° C |
*NOTICE: Stresses beyond those listed under “Absolute Maxi- |
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mum Ratings” may cause permanent damage to the |
Storage Temperature |
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C |
device. This is a stress rating only and functional |
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-65 C to + 150 |
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operation of the device at these or any other condi- |
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Voltage on Any Pin with |
-2.0V to + 7.0V(1) |
tions beyond those indicated in the operational sec- |
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Respect to Ground ........................................ |
tions of this specification is not implied. Exposure to |
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Voltage on A9 with |
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absolute maximum rating conditions for extended |
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-2.0V to + 14.0V(1) |
periods may affect device reliability. |
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Respect to Ground ..................................... |
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VPP Supply Voltage with |
-2.0V to + 14.0V(1) |
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Respect to Ground ...................................... |
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Note: |
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is |
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VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns. |
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3
0019M–EPROM–12/07
6. Operating Modes
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Mode/Pin |
CE |
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OE |
PGM |
Ai |
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VPP |
Outputs |
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Read |
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V |
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V |
IL |
X(1) |
Ai |
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X |
D |
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IL |
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OUT |
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Output Disable |
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X |
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VIH |
X |
X |
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X |
High Z |
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Standby |
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VIH |
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X |
X |
X |
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X(5) |
High Z |
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Rapid Program(2) |
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V |
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V |
IH |
V |
IL |
Ai |
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V |
PP |
D |
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IL |
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IN |
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PGM Verify |
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VIL |
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VIL |
VIH |
Ai |
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VPP |
DOUT |
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PGM Inhibit |
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VIH |
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X |
X |
X |
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VPP |
High Z |
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Product Identification(4) |
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A9 = VH(3) |
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V |
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V |
IL |
X |
A0 = V |
or V |
IL |
V |
CC |
Identification Code |
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IL |
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IH |
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A1 - A15 = VIL |
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Notes: 1. X can be VIL or VIH.
2.Refer to Programming Characteristics.
3.VH = 12.0 ± 0.5V.
4.Two identifier words may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled low (VIL) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word.
5.Standby VCC current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB.
7.DC and AC Operating Conditions for Read Operation
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AT27C1024 |
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-45 |
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-70 |
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Operating Temp. (Case) |
Ind. |
-40° C - 85° C |
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-40° C - 85° C |
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Auto. |
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VCC Power Supply |
5V ± 10% |
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5V ± 10% |
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8. DC and Operating Characteristics for Read Operation
Symbol |
Parameter |
Condition |
Min |
Max |
Units |
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ILI |
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Input Load Current |
VIN |
= 0V to VCC |
Ind. |
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±1 |
µA |
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Auto. |
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±5 |
µA |
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ILO |
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Output Leakage Current |
VOUT = 0V to VCC |
Ind. |
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±5 |
µA |
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Auto. |
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±10 |
µA |
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I |
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(2) |
V |
(1)) Read/Standby Current |
V |
= V |
CC |
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10 |
µA |
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PP1 |
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PP |
PP |
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ISB1 (CMOS), |
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= VCC ± 0.3V |
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100 |
µA |
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ISB |
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VCC(1) Standby Current |
CE |
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ISB2 (TTL), CE = 2.0 to VCC + 0.5V |
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1 |
mA |
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ICC |
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VCC Active Current |
f = 5 MHz, IOUT = 0 mA, |
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= VIL |
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30 |
mA |
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CE |
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VIL |
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Input Low Voltage |
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-0.6 |
0.8 |
V |
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VIH |
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Input High Voltage |
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2.0 |
VCC + 0.5 |
V |
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VOL |
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Output Low Voltage |
IOL = 2.1 mA |
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0.4 |
V |
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VOH |
Output High Voltage |
IOH = -400 µA |
2.4 |
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V |
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Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP..
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP..
4 AT27C1024 
0019M–EPROM–12/07
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