BDTIC www.BDTIC.com/ATMEL
Features
• Fast Read Access Time – 55 ns
• Low-power CMOS Operation
– 100 µA Max Standby
– 25 mA Max Active at 5 MHz
• JEDEC Standard Packages
– 32-lead PDIP
– 32-lead PLCC
– 32-lead TSOP
• 5V ± 10% Supply
• High-reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latch-up Immunity
• Rapid
• CMOS- and TTL-compatible Inputs and Outputs
• Integrated Product Identification Code
• Industrial and Automotive Temperature Ranges
• Green (Pb/Halide-free) Packaging Option
Programming Algorithm – 100 µs/Byte (Typical)
2-megabit
(256K x 8)
OTP EPROM
AT27C020
1. Description
The AT27C020 is a low-power, high-performance, 2,097,152-bit, one-time programmable read-only memory (OTP EPROM) organized as 256K by 8 bits. It requires only
one 5V power supply in normal read mode operation. Any byte can be accessed
in less than 55 ns, eliminating the need for speed-reducing WAIT states on highperformance microprocessor systems.
In read mode, the AT27C020 typically consumes 8 mA. Standby mode supply current
is typically less than 10 µA.
The AT27C020 is available in a choice of industry-standard JEDEC-approved onetime programmable (OTP) plastic PDIP, PLCC and TSOP packages. All devices feature two-line control (CE
contention.
With 256K bytes storage capability, the AT27C020 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media.
Atmel’s AT27C020 has additional features to ensure high quality and efficient production use. The Rapid
part and guarantees reliable programming. Programming time is typically only
100 µs/byte. The Integrated Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry-standard programming
equipment to select the proper programming algorithms and voltages.
Programming Algorithm reduces the time required to program the
, OE) to give designers the flexibility to prevent bus
0570G–EPROM–12/07
2. Pin Configurations
Pin Name Function
A0 - A17 Addresses
O0 - O7 Outputs
CE
OE
PGM
2.1 32-lead PLCC Top View
A12
A15
A16
VPP
VCC
PGM
A7
A6
A5
A4
A3
A2
A1
A0
O0
432
5
6
7
8
9
10
11
12
13
14151617181920
01
02
1
030405
GND
323130
A17
29
28
27
26
25
24
23
22
21
06
A14
A13
A8
A9
A11
OE
A10
CE
07
Chip Enable
Output Enable
Program Strobe
2.3 32-lead TSOP (Type 1) Top View
A11
A9
A8
A13
A14
A17
PGM
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
07
06
05
04
03
GND
02
01
O0
A0
A1
A2
A3
2.2 32-lead PDIP Top View
1
VPP
2
A16
3
A15
4
A12
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
13
O0
14
O1
15
O2
16
GND
2
AT27C020
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
PGM
A17
A14
A13
A8
A9
A11
OE
A10
CE
07
06
05
04
03
0570G–EPROM–12/07
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may
exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF highfrequency, low inherent inductance, ceramic capacitor should be utilized for each device. This
capacitor should be connected between the V
to the device as possible. Additionally, to stabilize the supply-voltage level on printed circuit
boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again
connected between the V
close as possible to the point where the power supply is connected to the array.
4. Block Diagram
AT27C020
and Ground terminals of the device, as close
CC
and Ground terminals. This capacitor should be positioned as
CC
5. Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on A9 with
Respect to Ground ......................................-2.0V to +14.0V
VPP Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V
Note: 1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
+ 0.75V DC, which may overshoot to +7.0V for pulses of less than 20 ns.
V
CC
(1)
(1)
(1)
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
0570G–EPROM–12/07
3
6. Operating Modes
Mode/Pin CE OE PGM Ai V
Read V
IL
Output Disable X V
Standby V
Rapid Program
(2)
PGM Verify V
PGM Inhibit V
Product Identification
(4)
IH
V
IL
IL
IH
V
IL
V
IL
IH
X X X X High-Z
V
IH
V
IL
XX X V
V
IL
(1)
X
Ai X D
X X X High-Z
V
IL
V
IH
X
Ai V
Ai V
A9 = V
(3)
H
A0 = VIH or V
A1 - A17 = V
IL
IL
Notes: 1. X can be VIL or VIH.
2. Refer to Programming Characteristics.
3. V
= 12.0 ± 0.5V.
H
4. Two identifier bytes may be selected. All Ai inputs are held low (V
low (V
) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
IL
) except A9, which is set to VH and A0, which is toggled
IL
7. DC and AC Operating Conditions for Read Operation
-55 -90
PP
PP
PP
PP
Outputs
OUT
D
IN
D
OUT
High-Z
X Identification Code
AT27C020
Operating Temperature (Case)
Ind. -40° C - 85° C-40° C - 85° C
Auto. -40° C - 125° C
Power Supply 5V ± 10% 5V ± 10%
V
CC
8. DC and Operating Characteristics for Read Operation
Symbol Parameter Condition Min Max Units
I
LI
I
LO
(2)
I
PP
I
SB
I
CC
V
IL
V
IH
V
OL
V
OH
Notes: 1. V
2. V
Input Load Current VIN = 0V to V
Output Leakage Current V
(1)
V
Read/Standby Current V
PP
(1)
V
Standby Current
CC
= 0V to V
OUT
= V
PP
CC
I
(CMOS), CE = VCC ± 0.3V 100 µA
SB1
(TTL), CE = 2.0 to V
I
SB2
VCC Active Current f = 5 MHz, I
Input Low Voltage -0.6 0.8 V
Input High Voltage 2.0 VCC + 0.5 V
Output Low Voltage I
= 2.1 mA 0.4 V
OL
Output High Voltage IOH = -400 µA 2.4 V
must be applied simultaneously or before V
CC
may be connected directly to VCC except during programming. The supply current would then be the sum of I
PP
(Com., Ind.) ±1.0 µA
CC
(Com., Ind.) ±5.0 µA
CC
±10 µA
+ 0.5V 1.0 mA
CC
= 0 mA, CE = V
OUT
, and removed simultaneously or after V
PP
IL
PP
.
25 mA
CC
and I
PP
.
4
AT27C020
0570G–EPROM–12/07
9. AC Characteristics for Read Operation
AT27C020
AT27C020
-55 -90
Symbol Parameter Condition
CE
t
t
t
t
t
ACC
CE
OE
DF
OH
(3)
(2)
(2)(3)
(4)(5)
Address to Output Delay
CE to Output Delay OE = V
OE to Output Delay CE = V
OE or CE H igh to Output Float,
Whichever Occurred First
Output Hold from Address, CE or OE,
Whichever Occurred First
= OE
= V
10. AC Waveforms for Read Operation
(1)
Min Max Min Max
Units
55 90 ns
IL
IL
IL
55 90 ns
20 35 ns
18 20 ns
70ns
Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE
may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE
may be delayed up to t
- tOE after the address is valid without impact on t
ACC
ACC
.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
0570G–EPROM–12/07
5
11. Input Test Waveforms and Measurement Levels
T
For -55 devices only:
3.0V
AC
DRIVING
LEVELS
, tF < 5 ns (10% to 90%)
t
R
1.5V
0.0V
AC
MEASUREMEN
LEVEL
For -90 devices only:
, tF < 20 ns (10% to 90%)
t
R
12. Output Test Load
Note: CL = 100 pF including jig capacitance except -55 devices, where CL = 30 pF.
13. Pin Capacitance
f = 1 MHz, T = 25° C
Symbol Typ Max Units Conditions
C
IN
C
OUT
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
(1)
48pFV
812pFV
IN
OUT
= 0V
= 0V
6
AT27C020
0570G–EPROM–12/07
AT27C020
14. Programming Waveforms
(1)
Notes: 1. The Input Timing reference is 0.8V for VIL and 2.0V for VIH.
2. t
and t
OE
3. When programming the AT27C020, a 0.1 µF capacitor is required across V
are characteristics of the device but must be accommodated by the programmer.
DFP
and ground to suppress voltage transients.
PP
0570G–EPROM–12/07
7
15. DC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits
Symbol Parameter Test Conditions
I
V
V
V
V
I
I
V
LI
IL
IH
OL
OH
CC2
PP2
ID
Input Load Current VIN = VIL, V
IH
Input Low Level -0.6 0.8 V
Input High Level 2.0 V
Output Low Voltage IOL = 2.1 mA 0.4 V
Output High Voltage IOH = -400 µA 2.4 V
VCC Supply Current (Program and Verify) 40 mA
VPP Supply Current CE = PGM = V
A9 Product Identification Voltage 11.5 12.5 V
16. AC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V,VPP = 13.0 ± 0.25V
Symbol Parameter Test Condition
t
AS
t
CES
t
OES
t
DS
t
AH
t
DH
t
DFP
t
VPS
t
VCS
t
PW
t
OE
t
PRT
Notes: 1. V
Address Setup Time
CE Setup Time 2 µs
OE Setup Time 2 µs
Input Rise and Fall Times:
Data Setup Time 2 µs
Address Hold Time 0 µs
Input Pulse Levels:
Data Hold Time 2 µs
OE High to Output Float Delay
VPP Setup Time 2 µs
V
Setup Time 2 µs
CC
PGM Program Pulse Width
(2)
Input Timing Reference Level:
(3)
Output Timing Reference Level:
Data Valid from OE 150 ns
VPP Pulse Rise Time During
Programming
must be applied simultaneously or before V
CC
PP
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven –
see timing diagram.
3. Program Pulse width tolerance is 100 µs ± 5%.
(1)
(10% to 90%) 20 ns
0.45V to 2.4V
0.8V to 2.0V
0.8V to 2.0V
and removed simultaneously or after V
UnitsMin Max
±10 µA
+ 1.0 V
CC
IL
20 mA
Limits
UnitsMin Max
2µs
0 130 ns
95 105 µs
50 ns
.
PP
17. Atmel’s AT27C020 Integrated Product Identification Code
Pins
Codes
Manufacturer 000011110 1E
Device Type 110000110 86
8
AT27C020
Hex DataA0 O7 O6 O5 O4 O3 O2 O1 O0
0570G–EPROM–12/07
18. Rapid Programming Algorithm
A 100 µs PGM pulse width is used to program. The address is set to the first location. VCC is
raised to 6.5V and V
PGM
pulse without verification. Then a verification/reprogramming loop is executed for each
address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses are
applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been
applied, the part is considered failed. After the byte verifies properly, the next address is
selected until all have been checked. V
are read again and compared with the original data to determine if the device passes or fails.
AT27C020
is raised to 13.0V. Each address is first programmed with one 100 µs
PP
is then lowered to 5.0V and VCC to 5.0V. All bytes
PP
0570G–EPROM–12/07
9
19. Ordering Information
19.1 Standard Package
(mA)
I
t
ACC
(ns)
55 25 0.1 AT27C020-55JI
90 25 0.1 AT27C020-90JI
CC
Ordering Code Package Operation RangeActive Standby
AT27C020-55PI
AT27C020-55TI
AT27C020-90PI
AT27C020-90TI
32J
32P6
32T
32J
32P6
32T
Industrial
(-40° C to 85° C)
Industrial
(-40° C to 85° C)
25 0.1 AT27C020-90JA
AT27C020-90PA
Note:
Not recommended for new designs. Use Green package option.
19.2 Green Package (Pb/Halide-free)
I
(mA)
t
ACC
(ns)
55 25 0.1 AT27C020-55JU
90 25 0.1 AT27C020-90JU
CC
Ordering Code Package Operation RangeActive Standby
AT27C020-55PU
AT27C020-55TU
AT27C020-90PU
AT27C020-90TU
32J
32P6
32J
32P6
32T
32J
32P6
32T
Automotive
(-40° C to 125° C)
Industrial
(-40° C to 85° C)
Industrial
(-40° C to 85° C)
Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32P6 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T 32-lead, Plastic Thin Small Outline Package (TSOP)
10
AT27C020
0570G–EPROM–12/07
20. Packaging Information
20.1 32J – PLCC
AT27C020
1.14(0.045) X 45˚
B
e
0.51(0.020)MAX
45˚ MAX (3X)
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
PIN NO. 1
IDENTIFIER
D1
D
D2
1.14(0.045) X 45˚
E1 E
0.318(0.0125)
0.191(0.0075)
E2
B1
A2
A1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2 9.906 – 10.922
E 14.859 – 15.113
E1 13.894 – 14.046 Note 2
E2 12.471 – 13.487
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
MIN
NOM
MAX
NOTE
10/04/01
2325 Orchard Parkway
R
San Jose, CA 95131
0570G–EPROM–12/07
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
32J
REV.
B
11
20.2 32P6 – PDIP
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
e
D
0º ~ 15º
eB
Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
TITLE
2325 Orchard Parkway
R
San Jose, CA 95131
32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A – – 4.826
A1 0.381 – –
D 41.783 – 42.291 Note 1
E 15.240 – 15.875
E1 13.462 – 13.970 Note 1
B 0.356 – 0.559
B1 1.041 – 1.651
L 3.048 – 3.556
C 0.203 – 0.381
eB 15.494 – 17.526
e 2.540 TYP
MIN
NOM
MAX
DRAWING NO.
32P6
NOTE
09/28/01
REV.
B
12
AT27C020
0570G–EPROM–12/07
20.3 32T – TSOP
AT27C020
PIN 1
Pin 1 Identifier
D1
D
e
E
b
A2
A
SEATING PLANE
A1
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
0º ~ 8º
L
COMMON DIMENSIONS
SYMBOL
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
c
L1
GAGE PLANE
(Unit of Measure = mm)
MIN
NOM
MAX
NOTE
2325 Orchard Parkway
R
San Jose, CA 95131
0570G–EPROM–12/07
TITLE
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
32T
10/18/01
REV.
B
13
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