BDTIC www.BDTIC.com/ATMEL
•Fast Read Access Time – 55 ns
•Low-power CMOS Operation
–100 µA Max Standby
–25 mA Max Active at 5 MHz
•JEDEC Standard Packages
–32-lead PDIP
–32-lead PLCC
–32-lead TSOP
•5V ± 10% Supply
•High-reliability CMOS Technology
–2,000V ESD Protection
–200 mA Latch-up Immunity
•Rapid Programming Algorithm – 100 µs/Byte (Typical)
•CMOSand TTL-compatible Inputs and Outputs
•Integrated Product Identification Code
•Industrial and Automotive Temperature Ranges
•Green (Pb/Halide-free) Packaging Option
The AT27C020 is a low-power, high-performance, 2,097,152-bit, one-time programmable read-only memory (OTP EPROM) organized as 256K by 8 bits. It requires only one 5V power supply in normal read mode operation. Any byte can be accessed in less than 55 ns, eliminating the need for speed-reducing WAIT states on highperformance microprocessor systems.
In read mode, the AT27C020 typically consumes 8 mA. Standby mode supply current is typically less than 10 µA.
The AT27C020 is available in a choice of industry-standard JEDEC-approved onetime programmable (OTP) plastic PDIP, PLCC and TSOP packages. All devices feature two-line control (CE, OE) to give designers the flexibility to prevent bus contention.
With 256K bytes storage capability, the AT27C020 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media.
Atmel’s AT27C020 has additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages.
2-megabit
(256K x 8) OTP EPROM
AT27C020
0570G–EPROM–12/07
Pin Name
A0 - A17
O0 - O7
CE
OE
PGM
2.132-lead PLCC Top View
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A12 |
A15 |
A16 |
VPP |
VCC |
PGM |
A17 |
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A7 |
4 |
3 |
2 |
1 |
32 |
31 |
30 |
A14 |
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5 |
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29 |
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A6 |
6 |
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28 |
A13 |
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A5 |
7 |
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27 |
A8 |
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A4 |
8 |
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26 |
A9 |
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A3 |
9 |
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25 |
A11 |
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A2 |
10 |
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24 |
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OE |
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A1 |
11 |
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23 |
A10 |
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A0 |
12 |
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22 |
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CE |
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O0 |
13 |
15 |
16 |
17 |
18 |
19 |
21 |
07 |
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14 |
20 |
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01 |
02 |
GND |
03 |
04 |
05 |
06 |
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2.232-lead PDIP Top View
VPP |
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1 |
32 |
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VCC |
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A16 |
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2 |
31 |
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PGM |
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A15 |
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3 |
30 |
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A17 |
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A12 |
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4 |
29 |
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A14 |
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A7 |
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5 |
28 |
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A13 |
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A6 |
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6 |
27 |
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A8 |
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A5 |
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7 |
26 |
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A9 |
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A4 |
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8 |
25 |
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A11 |
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A3 |
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9 |
24 |
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OE |
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A2 |
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10 |
23 |
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A10 |
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A1 |
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11 |
22 |
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CE |
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A0 |
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12 |
21 |
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07 |
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O0 |
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13 |
20 |
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06 |
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O1 |
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14 |
19 |
05 |
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O2 |
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15 |
18 |
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04 |
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GND |
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16 |
17 |
03 |
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2 AT27C020
Function
Addresses
Outputs
Chip Enable
Output Enable
Program Strobe
2.332-lead TSOP (Type 1) Top View
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A11 |
1 |
32 |
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OE |
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A9 |
2 |
31 |
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A10 |
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A8 |
3 |
30 |
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CE |
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A13 |
4 |
29 |
07 |
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A14 |
5 |
28 |
06 |
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A17 |
6 |
27 |
05 |
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7 |
26 |
04 |
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PGM |
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VCC |
8 |
25 |
03 |
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VPP |
9 |
24 |
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GND |
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A16 |
10 |
23 |
02 |
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A15 |
11 |
22 |
01 |
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A12 |
12 |
21 |
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O0 |
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A7 |
13 |
20 |
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A0 |
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A6 |
14 |
19 |
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A1 |
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A5 |
15 |
18 |
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A2 |
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A4 |
16 |
17 |
A3 |
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0570G–EPROM–12/07
AT27C020
Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF highfrequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply-voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.
5. |
Absolute Maximum Ratings* |
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Temperature under Bias |
................................ -55°C to +125°C |
*NOTICE: Stresses beyond those listed under “Absolute |
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Maximum Ratings” may cause permanent dam- |
Storage Temperature ..................................... |
-65°C to +150°C |
age to the device. This is a stress rating only and |
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functional operation of the device at these or any |
Voltage on Any Pin with |
-2.0V to +7.0V(1) |
other conditions beyond those indicated in the |
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Respect to Ground ......................................... |
operational sections of this specification is not |
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Voltage on A9 with |
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implied. Exposure to absolute maximum rating |
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-2.0V to +14.0V(1) |
conditions for extended periods may affect device |
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Respect to Ground ...................................... |
reliability. |
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VPP Supply Voltage with |
-2.0V to +14.0V(1) |
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Respect to Ground ....................................... |
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Note: |
1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is |
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VCC + 0.75V DC, which may overshoot to +7.0V for pulses of less than 20 ns. |
3
0570G–EPROM–12/07
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Mode/Pin |
CE |
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OE |
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PGM |
Ai |
VPP |
Outputs |
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Read |
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VIL |
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VIL |
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X(1) |
Ai |
X |
DOUT |
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Output Disable |
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X |
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VIH |
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X |
X |
X |
High-Z |
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Standby |
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VIH |
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X |
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X |
X |
X |
High-Z |
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Rapid Program(2) |
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V |
IL |
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V |
IH |
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V |
IL |
Ai |
V |
D |
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PP |
IN |
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PGM Verify |
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VIL |
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VIL |
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VIH |
Ai |
VPP |
DOUT |
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PGM Inhibit |
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VIH |
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X |
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X |
X |
VPP |
High-Z |
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A9 = V (3) |
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Product Identification(4) |
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H |
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VIL |
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VIL |
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X |
A0 = VIH or VIL |
X |
Identification Code |
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A1 - A17 = VIL |
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Notes: 1. X can be VIL or VIH. |
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2.Refer to Programming Characteristics.
3.VH = 12.0 ± 0.5V.
4.Two identifier bytes may be selected. All Ai inputs are held low (VIL) except A9, which is set to VH and A0, which is toggled low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
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AT27C020 |
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-55 |
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-90 |
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Operating Temperature (Case) |
Ind. |
-40° C - 85° C |
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-40° C - 85° C |
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Auto. |
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-40° C - 125° C |
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VCC Power Supply |
5V ± 10% |
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5V ± 10% |
Symbol |
Parameter |
Condition |
Min |
Max |
Units |
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ILI |
Input Load Current |
VIN = 0V to VCC (Com., Ind.) |
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±1.0 |
µA |
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ILO |
Output Leakage Current |
VOUT = 0V to VCC (Com., Ind.) |
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±5.0 |
µA |
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IPP(2) |
VPP(1) Read/Standby Current |
VPP = VCC |
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±10 |
µA |
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ISB1 (CMOS), |
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= VCC ± 0.3V |
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100 |
µA |
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ISB |
VCC(1) Standby Current |
CE |
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ISB2 (TTL), CE = 2.0 to VCC + 0.5V |
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1.0 |
mA |
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ICC |
VCC Active Current |
f = 5 MHz, IOUT = 0 mA, |
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= VIL |
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25 |
mA |
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CE |
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VIL |
Input Low Voltage |
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-0.6 |
0.8 |
V |
VIH |
Input High Voltage |
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2.0 |
VCC + 0.5 |
V |
VOL |
Output Low Voltage |
IOL = 2.1 mA |
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0.4 |
V |
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VOH |
Output High Voltage |
IOH = -400 µA |
2.4 |
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V |
Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. VPP may be connected directly to VCC except during programming. The supply current would then be the sum of ICC and IPP.
4 AT27C020
0570G–EPROM–12/07