ATMEL AT24CS256W-10SI-2.7, AT24CS256W-10SI-1.8, AT24CS256W-10SI, AT24CS256W-10SC-2.7, AT24CS256W-10SC-1.8 Datasheet

Features

•

One-Time Programmable (OTP) Feature

•

Low-Voltage and Standard-Voltage Operation

– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)

•

Internally Organized 16,384 x 8 and 32,768 x 8

•

2-Wire Serial Interface

•

Schmitt Trigger, Filtered Inputs for Noise Suppression

•

Bidirectional Data Transfer Protocol

•

1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility

•

Write Protect Pin for Hardware and Software Data Protection

•

64-Byte Page Write Mode (Partial Page Writes Allowed)

•

Self-Timed Write Cycle (5 ms typical)

•

High Reliability

– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
– ESD Protection: >4000V

•

Automotive Grade and Extended Temperature Devices Available

•

8-Pin JEDEC PDIP and 8-Pin JEDEC and EIAJ SOIC Packages

2-Wire Serial
EEPROMs
with Permanent
Software Write
Protect

Description

The AT24CS128/256 provides 131,072/262,144 bits of serial electrically erasable and
programmable read onl y mem ory ( EEPROM ) organi zed as 16,384/ 32,768 w ords of 8
bits each. The device’s cascadable feature allows up to 4 devices to share a common
2-wire bus. The device also features a one-time programmable 2048 bit array, which
once enabled, becomes r ead -only and can not be ove rwritten. If not enabled, the OTP
section will function as part of the normal memory array. The device is optimized for
use in many industri al and comm erc ial appli catio ns wher e low power and low v oltag e
operation are essential. The devices are available in space-saving 8-pin JEDEC PDIP
(AT24CS128/256), 8-pin EIAJ (AT24CS128/256), 8-pin JEDEC SOIC (AT24CS128)
packages. In addition, the en tire family is available in 5.0V (4.5V to 5.5V), 2.7 V (2.7V
to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Pin Configurations

Pin Name Function

A0 to A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect

A0
A1
A2

GND

8-Pin PDIP

1
2
3
4

8-Pin SOIC

8

VCC

7

WP

6

SCL

5

SDA

128K (16,384 x 8)
256K (32,768 x 8)

AT24CS128
AT24CS256
with Permanent
Software Write
Protect
Advanced
Information

A0
A1
A2

GND

1
2
3
4

VCC

8

WP

7

SCL

6

SDA

5

Rev. 1152A–09/98

1

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C

Storage Temperature.....................................-65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximum Operating Voltage........................................... 6.25V

DC Output Current........................................................5.0 mA

Block Diagram

A

2

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the dev ice . This is a stress ra ting onl y and
functional oper ati on of the device at these or an y
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or exten ded periods may af fect de vice
reliability.

Pin Description

SERIAL CLOCK (SCL):

edge clock data into each EEPROM device and negative
edge clock data out of each device.

SERIAL DATA (SDA):

serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0):

A0 pins are device address inputs that are hardwired or left
not connected for hardware compatibility with AT24C32/64.
When the pins are hardwired, as many as four 128K/256K
devices may be addres sed on a sing le bus syst em (devic e
addressing is discussed in detail under the Device
Addressing section). When the pins are not hardwired, the

2

AT24CS128/256

The SCL input is used to positive

The SDA pin is bidirectional for

The A1 and

default A

and A0 are zero. The A2 device address input is

1

a “don’t care” input.

WRITE PROTECT (WP):

The write protect input, when tied
to GND, allows normal write operations. Wh en WP is tied
high to V

, all write operat ions to the memory are inhib-

CC

ited. If left unconnected, WP is interna lly pulled down to
GND. Switching WP to V

prior to a write op eration cre-

CC

ates a soft ware write protect function.

Memory Organization

AT24CS128/256, 128K/2 56K SERIAL EEPROM:

128K/256K is internal ly organ ized as 25 6/51 2 pages of 64­bytes each. Random word addressing requires a 14/15-bit
data word address.

The

AT24CS128/256

Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.

Symbol Test Condition Max Units Conditions

C

I/O

C

IN

Input/Output Capacitance (SDA) 8 pF V

I/O

= 0V

Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V

Note: This parameter is characterized and is not 100% tested.

DC Characteristics

Applicable over recommended operating range from: T

= +1.8V to +5.5V (unless otherwise noted).

V

CC

Symbol Parameter Test Condition Min Typ Max Units

V
V
V
I
I

I

I

CC1

CC2

CC3

CC1

CC2

SB1

SB2

Supply Voltage 1.8 3.6 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC = 5.0V READ at 400 kHz 1.0 2.0 mA
Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA

= 1.8V

V

Standby Current
(1.8V option)

Standby Current
(2.7V option)

CC

V

= 3.6V 2.0

CC

V

= 2.7V

CC

VCC = 5.5V 5.0

= -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,

AI

0.2

= VCC or V

V

IN

SS

0.5

= VCC or V

V

IN

SS

µ

A

µ

A

I

I
I
V
V
V
V

SB3

LI

LO

IL

IH

OL2

OL1

Standby Current
(5.0V option)

Input Leakage Current VIN = V
Output Leakage Current V
Input Low Level
Input High Level

(Note:)

(Note:)

Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

= 4.5 - 5.5V VIN = VCC or V

V

CC

OUT

Note: VIL min and VIH max are reference only and are not tested

CC or VSS

= V

CC or VSS

SS

5.0

0.10 3.0

0.05 3.0

µ

µ
µ

-0.6 VCC x 0.3 V

VCC x 0.7 VCC + 0.5 V

A

A
A

3

AC Characteristics

Applicable over recommended operating ran ge fro m TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth­erwise noted). Test conditions are listed in Note 2.

1.8-volt 2.7-volt 5.0-volt

Symbol Parameter

f

SCL

t

LOW

t

HIGH

t

AA

t

BUF

t

HD.STA

t

SU.STA

t

HD.DAT

t

SU.DAT

t

R

t

F

t

SU.STO

t

DH

t

WR

Endurance

(1)

Clock Frequency, SCL 400 1000 1000 kHz
Clock Pulse Width Low 1.3 0.6 0.6 µs
Clock Pulse Width High 1.0 0.4 0.4 µs
Clock Low to Data Out Valid 0.1 0.9 0.05 0.55 0.05 0.55 µs
Time the bus must be free before a new

transmission can start

(1)

Start Hold Time 0.6 0.25 0.25 µs
Start Set-up Time 0.6 0.25 0.25 µs
Data In Hold Time 0 0 0 µs
Data In Set-up Time 100 100 100 ns
Inputs Rise Time
Inputs Fall Time

(1)

(1)

Stop Set-up Time 0.6 0.25 0.25 µs
Data Out Hold Time 50 50 50 ns
Write Cycle Time 20 10 10 ms

5.0V, 25°C, Page Mode 100K 100K 100K

Notes: 1. This parameter is characterized and is not 100% tested.

2. AC measurement conditions:
(connects to VCC): 1.3KΩ (2.7V, 5V), 10KΩ (1.8V)

R

L

Input pulse voltages: 0.3V

to 0.7V

CC

CC

Input rise and fall times: ≤50ns
Input and output timing reference voltages: 0.5V

CC

UnitsMinMaxMinMaxMinMax

1.2 0.5 0.5 µs

0.3 0.3 0.3 µs

300 100 100 ns

Write

Cycles

Device Operation

CLOCK and DATA TRANSITIONS:

mally pulled h ig h w ith an external devi ce . D ata on the SDA
pin may chan ge only dur ing SC L lo w ti me p eri ods (re fer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as defined
below.

START CONDITION:

A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia­gram).

STOP CONDITION:

A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).

4

AT24CS128/256

The SDA pin is nor-

ACKNOWLEDGE:

All addresses and data words are seri­ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.

STANDBY MODE:

The AT24CS128/256 features a low
power standby mode which is enabled: a) upon power-up
and b) after the r ecei pt of the STOP bit and the completi on
of any internal operations.

MEMORY RESET:

After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow­ing these steps: (a) Clock up to 9 cycles, (b) look for SDA
high in each cycle while SCL is high and then (c) create a
start condition as SDA is high.