ATMEL AT24C64W-10SI-2.7, AT24C64W-10SI-2.5, AT24C64W-10SI-1.8, AT24C64N-10SC-2.5, AT24C64N-10SC-1.8 Datasheet

Features

•

Low-Voltage and Standard-Voltage Operation

– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)

•

Low-Power Devices (ISB = 2

•

Internally Organized 4096 x 8, 8192 x 8

•

2-Wire Serial Interface

•

Schmitt Trigger, Filtered Inputs for Noise Suppression

•

Bidirectional Data Transfer Protocol

•

100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility

•

Write Protect Pin for Hardware Data Protection

•

32-Byte Page Write Mode (Partial Page Writes Allowed)

•

Self-Timed Write Cycle (10 ms max)

•

High Reliability

– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >3,000V

•

Automotive Grade and Extended Temperature Devices Available

•

8-Pin JEDEC PDIP, 8-Pin and 14-Pin JEDEC SOIC, 8-Pin EIAJ SOIC,
and 8-pin TSSOP Packages

µµµµ

A @ 5.5V) Available

2-Wire
Serial EEPROM

32K (4096 x 8)
64K (8192 x 8)

AT24C32

Description

The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and pro­grammable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common 2­wire bus. The device is optimized for use in many industrial and commercial applica­tions where low power and low voltag e operation are essential. The AT24C32/64 is
available in space sav ing 8-pin JEDEC PDIP , 8-pin and 14-pin JEDE C SOIC, 8-pi n
EIAJ SOIC, and 8-pin TSS O P pa ck ag es and is ac ce ss ed vi a a 2- wire s er ia l i nte rfa ce .
In addition, the entire family is available in 5.0V (4.5V to 5.5V ), 2.7V (2.7V to 5.5V),

2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

8-Pin PDIP

Pin Configurations

Pin Name Function

A0 to A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect

14-Pin SOIC

NC

A0
A1

NC

A2

GND

NC

1
2
3
4
5
6
7

14
13
12
11
10

NC
VCC
WP
NC
SCL

9

SDA

8

NC

GND

A0
A1
A2

GND

A0
A1
A2

GND

1

A0

2

A1

3

A2

4

8-Pin TSSOP

1
2
3
4

8-Pin SOIC

1
2
3
4

8

VCC

7

WP

6

SCL

5

SDA

8

VCC

7

WP

6

SCL

5

SDA

VCC

8

WP

7

SCL

6

SDA

5

AT24C64

2-Wire, 32K
Serial E

2

PROM

Rev. 0336F–08/98

1

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximum Operating Voltage........................................... 6.25V

DC Output Current........................................................5.0 mA

Block Diagram

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the de vic e. T his is a stres s r ating o nly an d
functional opera tion of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reli abi li ty.

Pin Description

SERIAL CLOCK (SCL):

edge clock data into each EEPROM device and negative
edge clock data out of each device.

SERIAL DATA (SDA):

serial data transfer. This pin is open-drain driv en and may
be wire-ORed with any number of other open-drain or open
collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0):

and A0 pins are device address inputs that are hard wired
or left not con nected for hardwar e compatibility with
AT24C16. When the pins are hardwired, as many as eight
32K/64K devices may be addressed on a single bus sys­tem (device addressing is discussed in detail under the

2

The SCL input is used to positive

The SDA pin is bidirectional for

The A2, A1

AT24C32/64

Device Addressing section). When the pins are not hard­wired, the default A

WRITE PROTECT (WP):

to GND, allows normal write operations. When WP is tied
high to V
(8/16K bits) of memory are inhibited. If left unconnected,
WP is internally pulled down to GND.

, all write operations to the upper quandrant

CC

, A1, and A0 are zero.

2

The write protect input, when tied

Memory Organization

AT24C32/64, 32K/6 4K SERI AL EE PROM:

internally organized as 2 56 pages of 32 bytes each. Ran­dom word addressing requires a 12/13 bit data word
address.

The 32K/64K is

AT24C32/64

Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MH z, VCC = +1.8V.

Symbol Test Condition Max Units Conditions

C

I/O

C

IN

Input/Out put Capacitance (SDA) 8 pF V

I/O

= 0V

Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

Note: 1. This parameter is characterized and is not 100% tested.

DC Characteristics

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,

= +1.8V to +5.5V (unless otherwise noted).

V

CC

Symbol Parameter Test Condition Min Typ Max Units

V
V
V
V
I
I

I

I

CC1

CC2

CC3

CC4

CC1

CC2

SB1

SB2

Supply Voltage 1.8 5.5 V
Supply Voltage 2.5 5.5 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA
Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA

Standby Current

(1.8V option)

Standby Current

(2.5V option)

= 1.8V

V

CC

V

= 5.5V 2.0

CC

V

= 2.5V

CC

VCC = 5.5V 2.0

= VCC or V

V

IN

= VCC or V

V

IN

SS

SS

0.1

0.5

µ

A

µ

A

I

SB3

I

SB4

I

LI

I

LO

V

IL

V

IH

V

OL2

V

OL1

Notes: 1. V

= 2.7V

V

Standby Current

(2.7V option)

Standby Current

(5V option)

CC

V

= 5.5V 2.0

CC

= VCC or V

V

IN

VCC = 4.5 - 5.5V VIN = VCC or V

Input Leakage Current VIN = V
Output Leakage Current V
Input Low Level
Input High Level

(1)

(1)

OUT

= V

CC or VSS

CC or VSS

SS

SS

20 35

0.10 3.0

0.05 3.0

-0.6 VCC x 0.3 V

VCC x 0.7 VCC + 0.5 V

0.5

Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

min and VIH max are reference only and are not tested.

IL

µ

A

µ

A

µ

A

µ

A

3

AC Characteristics

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100
pF (unless otherwise noted).

1.8-volt 2.7-, 2.5-volt 5.0-volt

Symbol Parameter

f

SCL

t

LOW

t

HIGH

t

I

t

AA

t

BUF

t

HD.STA

t

SU.STA

t

HD.DAT

t

SU.DAT

t

R

t

F

t

SU.STO

t

DH

t

WR

Endurance

Clock Frequency, SCL 100 100 400 kHz
Clock Pulse Width Low 4.7 4.7 1.2
Clock Pulse Width High 4.0 4.0 0.6
Noise Suppression Time

(1)

Clock Low to Data Out Valid 0.1 4.5 0.1 4.5 0.1 0.9
Time the bus must be free

before a new transmission can start

(1)

Start Hold Time 4.0 4.0 0.6
Start Set-up Time 4.7 4.7 0.6
Data In Hold Time 0 0 0
Data In Set-up Time 200 200 100 ns
Inputs Rise Time
Inputs Fall Time

(1)

(1)

Stop Set-up Time 4.7 4.7 0.6
Data Out Hold Time 100 100 50 ns
Write Cycle Time 20 10 10 ms

(1)

5.0V, 25°C, Page Mode 1M 1M 1M Write Cycles

Note: 1. This parameter is characterized and is not 100% tested.

100 100 50 ns

4.7 4.7 1.2

1.0 1.0 0.3

300 300 300 ns

UnitsMin Max Min Max Min Max

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

Device Operation

CLOCK and DATA TRANSITIONS:

mally pulled high wi th an ex ter na l dev ic e. Dat a o n t he SDA
pin may chan ge o nly duri ng S CL l ow t ime per iods (refe r t o
Data Validity timing diagram). Data changes during S CL
high periods will indicate a start or stop condition as
defined below.

START CONDITION:

A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia­gram).

STOP CONDITION:

A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will pla ce the EEPR OM in a standb y power
mode (refer to Start and Stop Definition timing diagram).

4

AT24C32/64

The SDA pin is nor-

ACKNOWLEDGE:

All addresses and data words are seri­ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.

STANDBY MODE:

The AT24C32/64 features a low power
standby mode which is enabled: a) upon power-up and b)
after the receipt of the STOP bit and the completi on of any
internal operations.

MEMORY RESET:

After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow­ing these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle
while SCL is high and then (c) create a start condition as
SDA is high.

Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O

Write Cycle T iming
SCL: Serial Clock, SDA: Serial Data I/O

AT24C32/64

(1)

t

WR

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write

cycle.

5