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AT24C512B
Datasheet
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Atmel AT24C512B Datasheet

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Features

1 2 3 4
8 7 6 5
A0 A1 A2
GND
VCC WP SCL SDA
1 2 3 4
8 7 6 5
A0 A1 A2
GND
VCC WP SCL SDA
1 2 3 4
8 7 6 5
VCC
WP
SCL
SDA
A0 A1 A2 GND
1 2 3 4
8 7 6 5
A0 A1 A2
GND
VCC WP SCL SDA
1 2
3
4
8
7 6 5
VCC
WP
SCL
SDA
A0 A1 A2 GND
• Low-voltage and Standard-voltage Operation
– 1.8v (V – 2.5v (VCC = 2.5V to 5.5V)
= 1.8V to 3.6V)
CC
• Internally Organized 65,536 x 8
• Two-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• 1 MHz (2.5V, 5.5V), 400 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 128-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
• High Reliability
– Endurance: 1,000,000 Write Cycles – Data Retention: 40 Years
• Lead-free/Halogen-free Devices
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-ball dBGA2, and
8-lead Ultra Thin Small Array (SAP) Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Die

Description

The AT24C512B provides 524,288 bits of serial electrically erasable and programma­ble read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-pin PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-ball dBGA2 and 8-lead Ultra Thin SAP packages. In addition, the entire family is available in 1.8V (1.8V to 3.6V) and 2.5V (2.5V to 5.5V) versions.
Two-wire Serial EEPROM
512K (65,536 x 8)
AT24C512B
with Three Device Address Inputs
Table 0-1. Pin Configurations
Pin Name Function
A0–A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
8-ball dBGA2
Bottom View
8-lead TSSOP
8-lead Ultra Thin SAP
Bottom View
8-lead PDIP
8-lead SOIC
Rev. 5297A–SEEPR–1/08
Absolute Maximum Ratings*
STA RT
STOP
LOGIC
VCC
GND
WP
SCL
SDA
A
2
A
1
A
0
SERIAL
CONTROL
LOGIC
EN
H.V. PUMP/TIMING
EEPROM
DATA RECOVERY
SERIAL MUX
X DEC
D
OUT
/ACK
LOGIC
COMP
LOAD
INC
DATA WORD
ADDR/COUNTER
Y DEC
R/W
D
OUT
D
IN
LOAD
DEVICE
ADDRESS
COMPARATOR
Operating Temperature..................................–55°C to +125°C
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 0-1. Block Diagram
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
AT24C512B
5297A–SEEPR–1/08

1. Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open­drain driven and may be wire-ORed with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight 512K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device Addressing,” page 8.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capaci­tive coupling that may appear during customer applications, Atmel connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the memory are inhib­ited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.
AT24C512B
®
recommends always
5297A–SEEPR–1/08
3

2. Memory Organization

AT24C512B, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of 128-bytes each. Random word
addressing requires a 16-bit data word address.
Table 2-1. Pin Capacitance
(1)
Applicable over recommended operating range from: TA = 25°C, f = 1.0 MHz, VCC = +1.8V to +5.5V
Symbol Test Condition Max Units Conditions
C
I/O
C
IN
Input/Output Capacitance (SDA) 8 pF V
I/O
= 0V
Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.
Table 2-2. DC Characteristics Applicable over recommended operating range from: T
Symbol Parameter Test Condition Min Typ Max Units
V
CC1
V
CC2
I
CC
I
CC
I
SB1
I
SB2
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Note: 1. VIL min and VIH max are reference only and are not tested.
Supply Voltage 1.8 3.6 V
Supply Voltage 2.5 5.5 V
Supply Current VCC = 5.0V READ at 400 kHz 2.0 mA
Supply Current VCC = 5.0V WRITE at 400 kHz 3.0 mA
V
= 1.8V
Standby Current
CC
= 3.6V 3.0 µA
V
CC
VCC = 2.5V
Standby Current
= 5.5V 6.0 µA
V
CC
Input Leakage Current VIN = V
Output Leakage Current
Input Low Level
Input High Level
(1)
(1)
V
OUT
CC or VSS
= V
CC or VSS
Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
= –40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)
AI
1.0 µA
= VCC or V
V
IN
SS
2.0 µA
VIN = VCC or V
SS
0.10 3.0 µA
0.05 3.0 µA
–0.6 VCC x 0.3 V
VCC x 0.7 VCC + 0.5 V
4
AT24C512B
5297A–SEEPR–1/08
Table 2-3. AC Characteristics (Industrial Temperature) Applicable over recommended operating range from T
= −40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-
AI
erwise noted). Test conditions are listed in Note 2.
AT24C512B
1.8-volt 2.5, 5.0-volt
Symbol Parameter
f
SCL
t
LOW
t
HIGH
t
i
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
Clock Frequency, SCL 400 1000 kHz
Clock Pulse Width Low 1.3 0.4 µs
Clock Pulse Width High 0.6 0.4 µs
Noise Suppression Time
(1)
Clock Low to Data Out Valid 0.05 0.9 0.05 0.55 µs
Time the bus must be free before a new transmission can start
(1)
Start Hold Time 0.6 0.25 µs
Start Set-up Time 0.6 0.25 µs
Data In Hold Time 0 0 µs
Data In Set-up Time 100 100 ns
Inputs Rise Time
Inputs Fall Time
(1)
(1)
Stop Set-up Time 0.6 0.25 µs
Data Out Hold Time 50 50 ns
Write Cycle Time 5 5 ms
(1)
25°C, Page Mode, 3.3V 1,000,000
Notes: 1. This parameter is ensured by characterization only.
2. AC measurement conditions: (connects to VCC): 1.3 kΩ (2.5V, 5V), 10 kΩ (1.8V)
R
L
Input pulse voltages: 0.3 VCC to 0.7 V
CC
Input rise and fall times: ≤ 50 ns Input and output timing reference voltages: 0.5 V
UnitsMin Max Min Max
100 50 ns
1.3 0.5 µs
0.3 0.3 µs
300 100 ns
Write
Cycles
CC
5297A–SEEPR–1/08
5

3. Device Operation

Start bit
Stop bitStart bitDummy Clock Cycles
SCL
SDA
12389
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 3-4 on page 8). Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 3-5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-
ure 3-5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl­edge that it has received each word.
STANDBY MODE: The AT24C512B features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations.
Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below. The device is ready for next communication after above steps have been completed.
Figure 3-1. Protocol Reset Condition
6
AT24C512B
5297A–SEEPR–1/08
Figure 3-2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
SCL
SDA IN
SDA OUT
t
F
t
HIGH
t
LOW
t
LOW
t
R
t
AA
t
DH
t
BUF
t
SU.STO
t
SU.DAT
t
HD.DAT
t
HD.STA
t
SU.STA
Figure 3-3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
AT24C512B
SCL
SDA
8th BIT
ACK
WORDn
(1)
t
wr
STOP
CONDITION
START
CONDITION
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
5297A–SEEPR–1/08
7
Figure 3-4. Data Validity
SDA
SCL
DATA STABLE DATA STABLE
DATA
CHANGE
SCL
DATA IN
DATA OUT
START ACKNOWLEDGE
9
8
1
Figure 3-5. Start and Stop Definition
SDA
SCL
Figure 3-6. Output Acknowledge
STA RT STOP
8
AT24C512B
5297A–SEEPR–1/08

4. Device Addressing

The 512K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 6-1 on page 10). The device address word con­sists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all two-wire EEPROM devices.
The 512K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is ini­tiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the device will return to a standby state.
DATA SECURITY: The AT24C512B has a hardware data protection scheme that allows the user to Write Protect the whole memory when the WP pin is at V

5. Write Operations

BYTE WRITE: A write operation requires two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t write cycle and the EEPROM will not respond until the write is complete (see Figure 6-2 on page
10).
AT24C512B
.
CC
, to the nonvolatile memory. All inputs are disabled during this
WR
PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 127 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must termi­nate the page write sequence with a stop condition (see Figure 6-3 on page 11).
The data word address lower 7 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the follow­ing byte is placed at the beginning of the same page. If more than 128 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address roll over during write is from the last byte of the current page to the first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The Read/Write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0”, allowing the read or write sequence to continue.
5297A–SEEPR–1/08
9

6. Read Operations

MSB
1 0 1 0 A
2
A
1
A0 R/W
LSB
Read operations are initiated the same way as write operations with the exception that the Read/Write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by “1”. This address stays valid between operations as long as the chip power is maintained. The address roll over during read is from the last byte of the last memory page, to the first byte of the first page.
Once the device address with the Read/Write select bit set to “1” is clocked in and acknowl­edged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (see Figure 6-4 on page 11).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the Read/Write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 6-5 on page 11).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran­dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll over and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 6-6 on page 11).
Figure 6-2. Byte Write
10
AT24C512B
Figure 6-1. Device Address
5297A–SEEPR–1/08
Figure 6-3. Page Write
Figure 6-4. Current Address Read
AT24C512B
Figure 6-5. Random Read
Figure 6-6. Sequential Read
5297A–SEEPR–1/08
11

Ordering Information

Ordering Code Voltage Package Operation Range
AT24C512B-PU (Bulk form only) 1.8 8P3
AT24C512B-PU25 (Bulk form only) 2.5 8P3
(1)
AT24C512BN-SH-B
AT24C512BN-SH-T
AT24C512BN-SH25-B
AT24C512BN-SH25-T
AT24C512BW-SH-B
AT24C512BW-SH-T
AT24C512BW-SH25-B
AT24C512BW-SH25-T
AT24C512B-TH-B
AT24C512B-TH-T
AT24C512B-TH25-B
AT24C512B-TH25-T
AT24C512BY7-YH-T
AT24C512BY7-YH25-T
AT24C512BU2-UU-T
AT24C512B-W-11
(NiPdAu Lead Finish) 1.8 8S1
(2)
(NiPdAu Lead Finish) 1.8 8S1
(1)
(NiPdAu Lead Finish) 2.5 8S1
(2)
(NiPdAu Lead Finish) 2.5 8S1
(1)
(NiPdAu Lead Finish) 1.8 8S2
(2)
(NiPdAu Lead Finish) 1.8 8S2
(1)
(NiPdAu Lead Finish) 2.5 8S2
(2)
(NiPdAu Lead Finish) 2.5 8S2
(1)
(NiPdAu Lead Finish) 1.8 8A2
(2)
(NiPdAu Lead Finish) 1.8 8A2
(1)
(NiPdAu Lead Finish) 2.5 8A2
(2)
(NiPdAu Lead Finish) 2.5 8A2
(2)
(NiPdAu Lead Finish) 1.8 8Y7
(2)
(NiPdAu Lead Finish) 2.5 8Y7
(2)
1.8 8U2-1
(3)
1.8 Die Sale Industrial Temperature
Lead-free/Halogen-free/
Industrial Temperature
(–40°C to 85°C)
(–40°C to 85°C)
Notes: 1. “-B” denotes bulk
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP and dBGA2 = 5K per reel. SAP = 3K per reel. EIAJ = 2K per reel.
3. Available in tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request.
Please contact Serial Interface Marketing.
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.200” Wide Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8Y7 8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP)
8U2-1 8-ball, die Ball Grid Array Package (dBGA2)
Options
–1.8 Low-voltage (1.8V to 3.6V)
–2.5 Low-voltage (2.5V to 5.5V)
12
AT24C512B
5297A–SEEPR–1/08
AT24C512B

7. Part marking scheme:

7.1 8-PDIP(1.8V)

TOP MARK Seal Year Y = SEAL YEAR WW = SEAL WEEK
| Seal Week 6: 2006 0: 2010 02 = Week 2
| | | 7: 2007 1: 2011 04 = Week 4
|---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: :
A T M L U Y W W 9: 2009 3: 2013 :: : :::: ::
|---|---|---|---|---|---|---|---| 50 = Week 50
2 F B 1 52 = Week 52
|---|---|---|---|---|---|---|---|
* Lot Number Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
| BOTTOM MARK
Pin 1 Indicator (Dot) No Bottom Mark

7.2 8-PDIP(2.5V)

TOP MARK Seal Year Y = SEAL YEAR WW = SEAL WEEK
| Seal Week 6: 2006 0: 2010 02 = Week 2
| | | 7: 2007 1: 2011 04 = Week 4
|---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: :
A T M L U Y W W 9: 2009 3: 2013 :: : :::: ::
|---|---|---|---|---|---|---|---| 50 = Week 50
2 F B 2 52 = Week 52
|---|---|---|---|---|---|---|---|
* Lot Number Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
| BOTTOM MARK
Pin 1 Indicator (Dot) No Bottom Mark
5297A–SEEPR–1/08
13

7.3 8-SOIC(1.8V)

TOP MARK
|---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: :
A T M L H Y W W 9: 2009 3: 2013 :: : :::: ::
|---|---|---|---|---|---|---|---| 50 = Week 50
2 F B 1 52 = Week 52
|---|---|---|---|---|---|---|---|
* Lot Number Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) No Bottom Mark
Seal Year Y = SEAL YEAR WW = SEAL WEEK | Seal Week 6: 2006 0: 2010 02 = Week 2
| | | 7: 2007 1: 2011 04 = Week 4
BOTTOM MARK

7.4 8-SOIC(2.5V)

TOP MARK
|---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: :
A T M L H Y W W 9: 2009 3: 2013 :: : :::: ::
|---|---|---|---|---|---|---|---| 50 = Week 50
2 F B 2 52 = Week 52
|---|---|---|---|---|---|---|---|
* Lot Number Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) No Bottom Mark
Seal Year Y = SEAL YEAR WW = SEAL WEEK | Seal Week 6: 2006 0: 2010 02 = Week 2
| | | 7: 2007 1: 2011 04 = Week 4
BOTTOM MARK
14
AT24C512B
5297A–SEEPR–1/08
AT24C512B

7.5 8-TSSOP(1.8V)

TOP MARK
Pin 1 Indicator (Dot) Y = SEAL YEAR WW = SEAL WEEK
| 6: 2006 0: 2010 02 = Week 2
|---|---|---|---| 7: 2007 1: 2011 04 = Week 4
* H Y W W 8: 2008 2: 2012 :: : :::: :
|---|---|---|---|---| 9: 2009 3: 2013 :: : :::: ::
2 F B 1 * 50 = Week 50
|---|---|---|---|---| 52 = Week 52
BOTTOM MARK
|---|---|---|---|---|---|---|
C 0 0
|---|---|---|---|---|---|---|
A A A A A A A
|---|---|---|---|---|---|---|
<- Pin 1 Indicator
Country of origin

7.6 8-TSSOP(2.5V)

TOP MARK
Pin 1 Indicator (Dot) Y = SEAL YEAR WW = SEAL WEEK
| 6: 2006 0: 2010 02 = Week 2
|---|---|---|---| 7: 2007 1: 2011 04 = Week 4
* H Y W W 8: 2008 2: 2012 :: : :::: :
|---|---|---|---|---| 9: 2009 3: 2013 :: : :::: ::
2 F B 2 * 50 = Week 50
|---|---|---|---|---| 52 = Week 52
BOTTOM MARK
|---|---|---|---|---|---|---|
C 0 0
|---|---|---|---|---|---|---|
A A A A A A A
|---|---|---|---|---|---|---|
<- Pin 1 Indicator
Country of origin
5297A–SEEPR–1/08
15

7.7 8-Ultra Thin SAP (1.8V)

TOP MARK Seal Year
| Seal Week Y = SEAL YEAR WW = SEAL WEEK
| | | 6: 2006 0: 2010 02 = Week 2 |---|---|---|---|---|---|---|---| 7: 2007 1: 2011 04 = Week 4
A T M L H Y W W 8: 2008 2: 2012 :: : :::: :
|---|---|---|---|---|---|---|---| 9: 2009 3: 2013 :: : :::: ::
2 F B 1 50 = Week 50
|---|---|---|---|---|---|---|---| 52 = Week 52
Lot Number
|---|---|---|---|---|---|---|---| * | Pin 1 Indicator (Dot)

7.8 8-Ultra Thin SAP (2.5V)

TOP MARK Seal Year
| Seal Week Y = SEAL YEAR WW = SEAL WEEK
| | | 6: 2006 0: 2010 02 = Week 2 |---|---|---|---|---|---|---|---| 7: 2007 1: 2011 04 = Week 4
A T M L H Y W W 8: 2008 2: 2012 :: : :::: :
|---|---|---|---|---|---|---|---| 9: 2009 3: 2013 :: : :::: ::
2 F B 2 50 = Week 50
|---|---|---|---|---|---|---|---| 52 = Week 52
Lot Number
|---|---|---|---|---|---|---|---| * | Pin 1 Indicator (Dot)
16
AT24C512B
5297A–SEEPR–1/08

7.8 dBGA2

AT24C512B
TOP MARK
LINE 1-------> 2FBU LINE 2-------> YMTC |<-- Pin 1 This Corner
P = Country of Origin
Y = ONE DIGIT YEAR CODE 4: 2004 7: 2007 5: 2005 8: 2008 6: 2006 9: 2009
M = SEAL MONTH (USE ALPHA DESIGNATOR A-L)
A = JANUARY
B = FEBRUARY
" " """"""" J = OCTOBER
K = NOVEMBER L = DECEMBER
TC = TRACE CODE (ATMEL LOT NUMBERS TO CORRESPOND WITH ATK TRACE CODE LOG BOOK)
5297A–SEEPR–1/08
17

8. Package Information

1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906
TITLE
DRAWING NO.
R
REV.
PO8U2-1
A
6/17/03
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch, Small Die Ball Grid Array Package (dBGA2)
A 0.81 0.91 1.00 A
1
0.15 0.20 0.25
A
2
0.40 0.45 0.50 b 0.25 0.30 0.35 D 2.35 BSC E 3.73 BSC
e
0.75 BSC
e1
0.74 REF d 0.75 BSC
d1
0.80 REF
5. Dimension 'b' is measured at the maximum solder ball diameter.
This drawing is for general information only.
d
A
SIDE VIEW
TOP VIEW
8 SOLDER BALLS
BOTTOM VIEW
1
A
B
C
D
2
(e1)
e
A1 BALL PAD CORNER
(d1)
5. b
A1
A2
D
A1 BALL PAD CORNER
E

U2-1 - dBGA2

18
AT24C512B
5297A–SEEPR–1/08

8P3 – PDIP

AT24C512B
D1
b3
4 PLCS
Top View
D
e
Side View
1
E
E1
N
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
b
b2
A2 A
SYMBOL
A
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
L
D1 0.005
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
MIN
NOM
–
MAX
–
0.210 2
–
–
3
NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicu
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
TITLE
2325 Orchard Parkway
R
San Jose, CA 95131
5297A–SEEPR–1/08
8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP)
lar to datum.
DRAWING NO.
8P3
01/09/02
REV.
B
19

8S1 – JEDEC SOIC

1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906
TITLE
DRAWING NO.
R
REV.
Note:
10/7/03
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC)
8S1 B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
A 1.35 – 1.75
B 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
∅ 0° – 8°
∅
Top View
End View
Side View
e
B
D
A
A1
N
E
1
C
E1
L
20
AT24C512B
5297A–SEEPR–1/08

8S2 - EIAJ SOIC

2325 Orchard Parkway San Jose, CA 95131
TITLE
DRAWING NO.
R
REV.
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
4/7/06
8S2
D
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 5
C 0.15 0.35 5
D 5.13 5.35
E1 5.18 5.40 2, 3
E 7.70 8.26
L 0.51 0.85
θ 0˚ 8˚
e 1.27 BSC 4
θθ
11
NN
EE
TOP VIEWTOP VIEW
CC
E1E1
END VIEWEND VIEW
AA
bb
LL
A1A1
ee
DD
SIDE VIEWSIDE VIEW
AT24C512B
5297A–SEEPR–1/08
21

8A2 – TSSOP

2325 Orchard Parkway San Jose, CA 95131
TITLE
DRAWING NO.
R
REV.
5/30/02
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2
B
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
22
AT24C512B
5297A–SEEPR–1/08

8Y7 – UTSAP

1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906
TITLE
DRAWING NO.
R
REV.
8Y7, 8-lead (6.00 x 4.90 mm Body) Ultra-Thin SOIC Array
Package (UTSAP) Y7
B
8Y7
10/13/05
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
A – – 0.60
A1 0.00 – 0.05
D 5.80 6.00 6.20
E 4.70 4.90 5.10
D1 3.30 3.40 3.50
E1 3.90 4.00 4.10
b 0.35 0.40 0.45
e 1.27 TYP
e1 3.81 REF
L 0.50 0.60 0.70
D1
PIN 1 ID
E1
L
b
e1
e
PIN 1 INDEX AREA
A
E
D
A1
A
AT24C512B
5297A–SEEPR–1/08
23

8U2-1 – dBGA2

1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906
TITLE
DRAWING NO.
R
REV.
PO8U2-1
A
6/17/03
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch, Small Die Ball Grid Array Package (dBGA2)
A 0.81 0.91 1.00 A
1 0.15 0.20 0.25
A
2 0.40 0.45 0.50
b 0.25 0.30 0.35 D 2.35 BSC E 3.73 BSC
e 0.75 BSC e1 0.74 REF
d 0.75 BSC
d1 0.80 REF
5. Dimension 'b' is measured at the maximum solder ball diameter.
This drawing is for general information only.
d
A
SIDE VIEW
TOP VIEW
8 SOLDER BALLS
BOTTOM VIEW
1
A
B
C
D
2
(e1)
e
A1 BALL PAD CORNER
(d1)
5.
b
A1
A2
D
A1 BALL PAD CORNER
E
24
AT24C512B
5297A–SEEPR–1/08

Revision History

Doc. Rev. Date Comments
AT24C512B product with date code 2008 work week 14 (814) or later
5297A 1/2008
supports 5Vcc operation Initial document release
AT24C512B
5297A–SEEPR–1/08
25
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5297A–SEEPR–1/08
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