Features
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
• Low-voltage and Standard-voltage Operation
– 1.8v (V
– 2.5v (VCC = 2.5V to 5.5V)
= 1.8V to 3.6V)
CC
• Internally Organized 65,536 x 8
• Two-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (2.5V, 5.5V), 400 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 128-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
• High Reliability
– Endurance: 1,000,000 Write Cycles
– Data Retention: 40 Years
• Lead-free/Halogen-free Devices
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-ball dBGA2, and
8-lead Ultra Thin Small Array (SAP) Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Die
Description
The AT24C512B provides 524,288 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each. The
device’s cascadable feature allows up to eight devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space-saving 8-pin PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP,
8-ball dBGA2 and 8-lead Ultra Thin SAP packages. In addition, the entire family is
available in 1.8V (1.8V to 3.6V) and 2.5V (2.5V to 5.5V) versions.
Two-wire Serial
EEPROM
512K (65,536 x 8)
AT24C512B
with Three Device Address Inputs
Table 0-1. Pin Configurations
Pin Name Function
A0–A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
8-ball dBGA2
Bottom View
8-lead TSSOP
8-lead Ultra Thin SAP
Bottom View
8-lead PDIP
8-lead SOIC
Rev. 5297A–SEEPR–1/08
Absolute Maximum Ratings*
STA RT
STOP
LOGIC
VCC
GND
WP
SCL
SDA
A
2
A
1
A
0
SERIAL
CONTROL
LOGIC
EN
H.V. PUMP/TIMING
EEPROM
DATA RECOVERY
SERIAL MUX
X DEC
D
OUT
/ACK
LOGIC
COMP
LOAD
INC
DATA WORD
ADDR/COUNTER
Y DEC
R/W
D
OUT
D
IN
LOAD
DEVICE
ADDRESS
COMPARATOR
Operating Temperature..................................–55°C to +125°C
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 0-1. Block Diagram
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
2
AT24C512B
5297A–SEEPR–1/08
1. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open collector
devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs
that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices.
When the pins are hardwired, as many as eight 512K devices may be addressed on a single bus
system. (Device addressing is discussed in detail under “Device Addressing,” page 8.) A device
is selected when a corresponding hardware and software match is true. If these pins are left
floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel
connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends
using 10kΩ or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write
operations. When WP is connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to
capacitive coupling that may appear during customer applications, Atmel recommends always
connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends
using 10kΩ or less.
AT24C512B
®
recommends always
5297A–SEEPR–1/08
3
2. Memory Organization
AT24C512B, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of 128-bytes each. Random word
addressing requires a 16-bit data word address.
Table 2-1. Pin Capacitance
(1)
Applicable over recommended operating range from: TA = 25°C, f = 1.0 MHz, VCC = +1.8V to +5.5V
Symbol Test Condition Max Units Conditions
C
I/O
C
IN
Input/Output Capacitance (SDA) 8 pF V
I/O
= 0V
Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.
Table 2-2. DC Characteristics
Applicable over recommended operating range from: T
Symbol Parameter Test Condition Min Typ Max Units
V
CC1
V
CC2
I
CC
I
CC
I
SB1
I
SB2
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Note: 1. VIL min and VIH max are reference only and are not tested.
Supply Voltage 1.8 3.6 V
Supply Voltage 2.5 5.5 V
Supply Current VCC = 5.0V READ at 400 kHz 2.0 mA
Supply Current VCC = 5.0V WRITE at 400 kHz 3.0 mA
V
= 1.8V
Standby Current
CC
= 3.6V 3.0 µA
V
CC
VCC = 2.5V
Standby Current
= 5.5V 6.0 µA
V
CC
Input Leakage Current VIN = V
Output Leakage
Current
Input Low Level
Input High Level
(1)
(1)
V
OUT
CC or VSS
= V
CC or VSS
Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
= –40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)
AI
1.0 µA
= VCC or V
V
IN
SS
2.0 µA
VIN = VCC or V
SS
0.10 3.0 µA
0.05 3.0 µA
–0.6 VCC x 0.3 V
VCC x 0.7 VCC + 0.5 V
4
AT24C512B
5297A–SEEPR–1/08
Table 2-3. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from T
= −40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-
AI
erwise noted). Test conditions are listed in Note 2.
AT24C512B
1.8-volt 2.5, 5.0-volt
Symbol Parameter
f
SCL
t
LOW
t
HIGH
t
i
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
Clock Frequency, SCL 400 1000 kHz
Clock Pulse Width Low 1.3 0.4 µs
Clock Pulse Width High 0.6 0.4 µs
Noise Suppression Time
(1)
Clock Low to Data Out Valid 0.05 0.9 0.05 0.55 µs
Time the bus must be free before
a new transmission can start
(1)
Start Hold Time 0.6 0.25 µs
Start Set-up Time 0.6 0.25 µs
Data In Hold Time 0 0 µs
Data In Set-up Time 100 100 ns
Inputs Rise Time
Inputs Fall Time
(1)
(1)
Stop Set-up Time 0.6 0.25 µs
Data Out Hold Time 50 50 ns
Write Cycle Time 5 5 ms
(1)
25°C, Page Mode, 3.3V 1,000,000
Notes: 1. This parameter is ensured by characterization only.
2. AC measurement conditions:
(connects to VCC): 1.3 kΩ (2.5V, 5V), 10 kΩ (1.8V)
R
L
Input pulse voltages: 0.3 VCC to 0.7 V
CC
Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 V
UnitsMin Max Min Max
100 50 ns
1.3 0.5 µs
0.3 0.3 µs
300 100 ns
Write
Cycles
CC
5297A–SEEPR–1/08
5
3. Device Operation
Start bit
Stop bitStart bitDummy Clock Cycles
SCL
SDA
12389
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.
Data on the SDA pin may change only during SCL low time periods (see Figure 3-4 on page 8).
Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 3-5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-
ure 3-5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE: The AT24C512B features a low power standby mode which is enabled: a)
upon power-up and b) after the receipt of the STOP bit and the completion of any internal
operations.
Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire
part can be protocol reset by following these steps: (a) Create a start bit condition, (b)
clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below.
The device is ready for next communication after above steps have been completed.
Figure 3-1. Protocol Reset Condition
6
AT24C512B
5297A–SEEPR–1/08
Figure 3-2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
SCL
SDA IN
SDA OUT
t
F
t
HIGH
t
LOW
t
LOW
t
R
t
AA
t
DH
t
BUF
t
SU.STO
t
SU.DAT
t
HD.DAT
t
HD.STA
t
SU.STA
Figure 3-3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
AT24C512B
SCL
SDA
8th BIT
ACK
WORDn
(1)
t
wr
STOP
CONDITION
START
CONDITION
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
5297A–SEEPR–1/08
7
Figure 3-4. Data Validity
SDA
SCL
DATA STABLE DATA STABLE
DATA
CHANGE
SCL
DATA IN
DATA OUT
START ACKNOWLEDGE
9
8
1
Figure 3-5. Start and Stop Definition
SDA
SCL
Figure 3-6. Output Acknowledge
STA RT STOP
8
AT24C512B
5297A–SEEPR–1/08
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