ATMEL AT24C512 User Manual

Features

•Low-voltage and Standard-voltage Operation

–2.7 (VCC = 2.7V to 5.5V)

–1.8 (VCC = 1.8V to 3.6V)

•Internally Organized 65,536 x 8

•Two-wire Serial Interface

•Schmitt Triggers, Filtered Inputs for Noise Suppression

•Bidirectional Data Transfer Protocol

•1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility

•Write Protect Pin for Hardware and Software Data Protection

•128-byte Page Write Mode (Partial Page Writes Allowed)

•Self-timed Write Cycle (5 ms Max)

•High Reliability

–Endurance: 100,000 Write Cycles

–Data Retention: 40 Years

•Automotive Grade, Extended Temperature and Lead-free/Halogen-free Devices Available

•8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead LAP, 8-lead SAP and 8-ball dBGA2 Packages

•Die Sales: Wafer Form, Waffle Pack and Bumped Die

Description

The AT24C512 provides 524,288 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s cascadable feature allows up to four devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where lowpower and low-voltage operation are essential. The devices are available in spacesaving 8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Table 1. Pin Configurations						8-lead TSSOP															8-lead PDIP
Pin Name		Function
						A0		1	8					VCC					A0			1		8		VCC
A0–A1		Address Inputs
						A1		2	7					WP					A1			2		7		WP
SDA		Serial Data
						NC		3	6					SCL				NC				3		6		SCL
						GND		4	5					SDA				GND				4		5		SDA
SCL		Serial Clock Input
WP		Write Protect												8-lead SOIC
NC		No Connect
											A0				1	8					VCC
											A1				2	7					WP
										NC					3	6					SCL
		8-ball dBGA2							GND						4	5					SDA
						8-lead Leadless Array															8-lead SAP
																		VCC								A0
	VCC		8	1	A0	VCC								A0							8			1
								8			1							WP							A1
	WP		7	2	A1	WP							A1								7			2
								7			2							SCL								NC
	SCL		6	3	NC	SCL								NC							6			3
								6			3							SDA							GND
	SDA		5	4	GND	SDA							GND								5			4
								5			4
		Bottom View																			Bottom View
								Bottom View

Two-wire Serial

EEPROM

512K (65,536 x 8)

AT24C512

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1

Absolute Maximum Ratings*

..................................Operating Temperature	–55°C to +125°C	*NOTICE: Stresses beyond those listed under “Absolute
		Maximum Ratings” may cause permanent dam-
Storage Temperature .....................................	–65°C to +150°C	age to the device. This is a stress rating only and
		functional operation of the device at these or any
Voltage on Any Pin		other conditions beyond those indicated in the
with Respect to Ground ....................................	–1.0V to +7.0V	operational sections of this specification is not
Maximum Operating Voltage	6.25V	implied. Exposure to absolute maximum rating
		conditions for extended periods may affect device
DC Output Current	5.0 mA	reliability.

Figure 1. Block Diagram

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AT24C512

Pin Description

Memory Organization

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.

DEVICE/ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other AT24Cxx devices. When the pins are hardwired, as many as four 512K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section. If the pins are left floating, the A1 and A0 pins will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting the address pins to GND.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected high to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting the pin to GND. Switching WP to VCC prior to a write operation creates a software write protect function.

AT24C512, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of 128-bytes each. Random word addressing requires a 16-bit data word address.

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Table 2. Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V

Symbol		Test Condition	Max	Units	Conditions
CI/O		Input/Output Capacitance (SDA)	8	pF	VI/O = 0V
CIN		Input Capacitance (A0, A1, SCL)	6	pF	VIN = 0V
Note: 1.	This parameter is characterized and is not 100% tested.

Table 3. DC Characteristics

Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted)

Symbol			Parameter	Test Condition			Min		Typ	Max	Units
VCC1			Supply Voltage				1.8			3.6	V
VCC2			Supply Voltage				2.7			5.5	V
VCC3			Supply Voltage				4.5			5.5	V
ICC1			Supply Current	VCC = 5.0V	READ at 400 kHz				1.0	2.0	mA
ICC2			Supply Current	VCC = 5.0V	WRITE at 400 kHz				2.0	3.0	mA
ISB1			Standby Current	VCC = 1.8V	VIN = VCC or VSS					1.0	µA
			(1.8V option)	VCC = 3.6V						3.0
ISB2			Standby Current	VCC = 2.7V	VIN = VCC or VSS					2.0	µA
			(2.7V option)	VCC = 5.5V						6.0
ISB3			Standby Current	VCC = 4.5 - 5.5V	VIN = VCC or VSS					6.0	µA
			(5.0V option)
ILI			Input Leakage Current	VIN = VCC or VSS					0.10	3.0	µA
ILO			Output Leakage	VOUT = VCC or VSS					0.05	3.0	µA
			Current
VIL			Input Low Level(1)				–0.6			VCC x 0.3	V
V	IH		Input High Level(1)			V	CC	x 0.7		V + 0.5	V
										CC
VOL2			Output Low Level	VCC = 3.0V	IOL = 2.1 mA					0.4	V
VOL1			Output Low Level	VCC = 1.8V	IOL = 0.15 mA					0.2	V
Note: 1.		VIL min and VIH max are reference only and are not tested.

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AT24C512

Table 4. AC Characteristics

Applicable over recommended operating range from TA = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless otherwise noted) Test conditions are listed in Note 2.

		1.8 Volt		2.7 Volt		5.0 Volt
Symbol	Parameter	Min	Max	Min	Max	Min	Max	Units
fSCL	Clock Frequency, SCL		100		400		1000	kHz
tLOW	Clock Pulse Width Low	4.7		1.3		0.4		µs
tHIGH	Clock Pulse Width High	4.0		1.0		0.4		µs
tAA	Clock Low to Data Out Valid	0.1	4.5	0.05	0.9	0.05	0.55	µs
tBUF	Time the bus must be free before a	4.7		1.3		0.5		µs
	(1)
	new transmission can start
tHD.STA	Start Hold Time	4.0		0.6		0.25		µs
tSU.STA	Start Set-up Time	4.7		0.6		0.25		µs
tHD.DAT	Data In Hold Time	0		0		0		µs
tSU.DAT	Data In Set-up Time	200		100		100		ns
tR	Inputs Rise Time(1)		1.0		0.3		0.3	µs
tF	Inputs Fall Time(1)		300		300		100	ns
tSU.STO	Stop Set-up Time	4.7		0.6		0.25		µs
tDH	Data Out Hold Time	100		50		50		ns
tWR	Write Cycle Time		20 or 5(3)		10 or 5(3)		10 or 5(3)	ms
Endurance(1)	5.0V, 25°C, Page Mode	100K		100K		100K		Write Cycles

Notes: 1. This parameter is characterized and is not 100% tested.

2.AC measurement conditions:

RL (connects to VCC): 1.3 kΩ (2.7V, 5V), 10 kΩ (1.8V)

Input pulse voltages: 0.3VCC to 0.7VCC Input rise and fall times: ≤50 ns

Input and output timing reference voltages: 0.5VCC

3.The Write Cycle Time of 5 ms only applies to the AT24C512 devices bearing the process letter “A” on the package (the mark is located in the lower right corner on the top side of the package).

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Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 8).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 8).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.

STANDBY MODE: The AT24C512 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any twowire part can be reset by following these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then

(c) create a start condition as SDA is high.

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