ATMEL AT24C512 User Manual

Features

• Low-voltage and Standard-voltage Operation

– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (V

= 1.8V to 3.6V)

CC

• Internally Organized 65,536 x 8

• Two-wire Serial Interface

• Schmitt Triggers, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility

• Write Protect Pin for Hardware and Software Data Protection

• 128-byte Page Write Mode (Partial Page Writes Allowed)

• Self-timed Write Cycle (5 ms Max)

• High Reliability

– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years

• Automotive Grade, Extended Temperature and Lead-free/Halogen-free

Devices Available

• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP,

8-lead LAP, 8-lead SAP and 8-ball dBGA2 Packages

• Die Sales: Wafer Form, Waffle Pack and Bumped Die

Description

The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s
cascadable feature allows up to four devices to share a common two-wire bus. The
device is optimized for use in many industrial and commercial applications where low­power and low-voltage operation are essential. The devices are available in space­saving 8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead
Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is avail­able in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Two-wire Serial
EEPROM

512K (65,536 x 8)

AT24C512

Table 1. Pin Configurations

Pin Name Function

A0–A1 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

8-ball dBGA2

1

8

VCC

7

WP

6

SCL

5

SDA

Bottom View

A0

2

A1

3

NC

4

GND

8-lead TSSOP

8
7
6
5

A0
A1

NC

GND

VCC
WP
SCL
SDA

A0
A1

NC

GND

1
2
3
4

8-lead Leadless Array

VCC

WP

SCL

SDA

8
7
6
5

A0

1

A1

2

NC

3

GND

4

Bottom View

GND

8-lead SOIC

1
2
3
4

8
7
6
5

VCC

SCL

SDA

8-lead PDIP

1

A0

2

A1

3

NC

4

VCC
WP
SCL
SDA

8-lead SAP

8

WP

7
6
5

Bottom View

8

VCC

7

WP

6

SCL

5

SDA

A0

1

A1

2

NC

3

GND

4

Rev. 1116M–SEEPR–05/05

1

Absolute Maximum Ratings*

Operating Temperature..................................–55°C to +125°C

Storage Temperature .....................................–65°C to +150°C

Voltage on Any Pin

with Respect to Ground ....................................–1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Figure 1. Block Diagram

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

2

AT24C512

1116M–SEEPR–05/05

AT24C512

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.

DEVICE/ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are
hardwired or left not connected for hardware compatibility with other AT24Cxx devices.
When the pins are hardwired, as many as four 512K devices may be addressed on a
single bus system (device addressing is discussed in detail under the Device Address-
ing section. If the pins are left floating, the A1 and A0 pins will be internally pulled down
to GND if the capacitive coupling to the circuit board V
>3 pF, Atmel recommends connecting the address pins to GND.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor­mal write operations. When WP is connected high to V
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND if the capacitive coupling to the circuit board V
>3 pF, Atmel recommends connecting the pin to GND. Switching WP to V
write operation creates a software write protect function.

plane is <3 pF. If coupling is

CC

, all write operations to the

CC

plane is <3 pF. If coupling is

CC

prior to a

CC

Memory Organization AT24C512, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of

128-bytes each. Random word addressing requires a 16-bit data word address.

1116M–SEEPR–05/05

3

Table 2. Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V

Symbol Test Condition Max Units Conditions

C

I/O

C

IN

Input/Output Capacitance (SDA) 8 pF V

Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V

I/O

= 0V

Note: 1. This parameter is characterized and is not 100% tested.

Table 3. DC Characteristics
Applicable over recommended operating range from: T
V

= +1.8V to +5.5V (unless otherwise noted)

CC

Symbol Parameter Test Condition Min Typ Max Units

V

CC1

V

CC2

V

CC3

I

CC1

I

CC2

I

SB1

I

SB2

I

SB3

I

LI

I

LO

V

IL

V

IH

V

OL2

V

OL1

Note: 1. V

Supply Voltage 1.8 3.6 V

Supply Voltage 2.7 5.5 V

Supply Voltage 4.5 5.5 V

Supply Current VCC = 5.0V READ at 400 kHz 1.0 2.0 mA

Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA

= 1.8V

V

Standby Current
(1.8V option)

Standby Current
(2.7V option)

Standby Current
(5.0V option)

Input Leakage Current VIN = V

Output Leakage
Current

Input Low Level

Input High Level

(1)

(1)

CC

= 3.6V 3.0

V

CC

= 2.7V

V

CC

= 5.5V 6.0

V

CC

= 4.5 - 5.5V VIN = VCC or V

V

CC

CC or VSS

= V

V

OUT

CC or VSS

Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V

Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

min and VIH max are reference only and are not tested.

IL

= –40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,

AI

1.0 µA

= VCC or V

V

IN

SS

2.0 µA

VIN = VCC or V

SS

SS

6.0 µA

0.10 3.0 µA

0.05 3.0 µA

–0.6 VCC x 0.3 V

VCC x 0.7 VCC + 0.5 V

4

AT24C512

1116M–SEEPR–05/05

Table 4. AC Characteristics
Applicable over recommended operating range from T
erwise noted) Test conditions are listed in Note 2.

Symbol Parameter

f

SCL

t

LOW

t

HIGH

t

AA

t

BUF

t

HD.STA

t

SU.STA

t

HD.DAT

t

SU.DAT

t

R

t

F

t

SU.STO

t

DH

t

WR

Endurance

Clock Frequency, SCL 100 400 1000 kHz

Clock Pulse Width Low 4.7 1.3 0.4 µs

Clock Pulse Width High 4.0 1.0 0.4 µs

Clock Low to Data Out Valid 0.1 4.5 0.05 0.9 0.05 0.55 µs

Time the bus must be free before a
new transmission can start

(1)

Start Hold Time 4.0 0.6 0.25 µs

Start Set-up Time 4.7 0.6 0.25 µs

Data In Hold Time 0 0 0 µs

Data In Set-up Time 200 100 100 ns

Inputs Rise Time

Inputs Fall Time

(1)

(1)

Stop Set-up Time 4.7 0.6 0.25 µs

Data Out Hold Time 100 50 50 ns

Write Cycle Time 20 or 5

(1)

5.0V, 25°C, Page Mode 100K 100K 100K Write Cycles

AT24C512

= –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-

A

1.8 Volt 2.7 Volt 5.0 Volt

UnitsMin Max Min Max Min Max

4.7 1.3 0.5 µs

1.0 0.3 0.3 µs

300 300 100 ns

(3)

10 or 5

(3)

10 or 5

(3)

ms

Notes: 1. This parameter is characterized and is not 100% tested.

2. AC measurement conditions:
(connects to VCC): 1.3 kΩ (2.7V, 5V), 10 kΩ (1.8V)

R

L

Input pulse voltages: 0.3VCC to 0.7V

CC

Input rise and fall times: ≤50 ns
Input and output timing reference voltages: 0.5V

CC

3. The Write Cycle Time of 5 ms only applies to the AT24C512 devices bearing the process letter “A” on the package (the mark

is located in the lower right corner on the top side of the package).

1116M–SEEPR–05/05

5

Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-

nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 8).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 8).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.

STANDBY MODE: The AT24C512 features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two­wire part can be reset by following these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.

6

AT24C512

1116M–SEEPR–05/05

Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

SCL

AT24C512

SDA

WORDn

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

8th BIT

ACK

STOP

CONDITION

(1)

t

wr

START

CONDITION

Figure 4. Data Validity

1116M–SEEPR–05/05

7

Figure 5. Start and Stop Definition

Figure 6. Output Acknowledge

8

AT24C512

1116M–SEEPR–05/05

AT24C512

Device Addressing The 512K EEPROM requires an 8-bit device address word following a start condition to

enable the chip for a read or write operation (see Figure 7 on page 10). The device
address word consists of a mandatory “1”, “0” sequence for the first five most significant
bits as shown. This is common to all two-wire EEPROM devices.

The 512K uses the two device address bits A1, A0 to allow as many as four devices on
the same bus. These bits must compare to their corresponding hardwired input pins.
The A1 and A0 pins use an internal proprietary circuit that biases them to a logic low
condition if the pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read opera­tion is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a “0”. If a compare is
not made, the device will return to a standby state.

DATA SECURITY: The AT24C512 has a hardware data protection scheme that allows
the user to Write Protect the whole memory when the WP pin is at V

Write Operations BYTE WRITE: A write operation requires two 8-bit data word addresses following the

device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a “0” and then clock in the first 8-bit data word. Following receipt
of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a
microcontroller, then must terminate the write sequence with a stop condition. At this
time the EEPROM enters an internally-timed write cycle, t
All inputs are disabled during this write cycle and the EEPROM will not respond until the
write is complete (see Figure 8 on page 11).

, to the nonvolatile memory.

WR

CC

.

PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes.

A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 127
more data words. The EEPROM will respond with a “0” after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (see
Figure 9 on page 11).

The data word address lower 7 bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 128 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten. The address roll over during write is from the
last byte of the current page to the first byte of the same page.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send­ing a start condition followed by the device address word. The Read/Write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a “0”, allowing the read or write sequence to continue.

1116M–SEEPR–05/05

9

Read Operations Read operations are initiated the same way as write operations with the exception that

the Read/Write select bit in the device address word is set to “1”. There are three read
operations: current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by “1”. This
address stays valid between operations as long as the chip power is maintained. The
address roll over during read is from the last byte of the last memory page, to the first
byte of the first page.

Once the device address with the Read/Write select bit set to “1” is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input “0” but does generate a following
stop condition (see Figure 10 on page 11).

RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the Read/Write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a “0” but does generate a following stop condition (see Figure 11 on page 11).

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will roll over and the sequential
read will continue. The sequential read operation is terminated when the microcontroller
does not respond with a “0” but does generate a following stop condition (see Figure 12
on page 12).

Figure 7. Device Address

10

AT24C512

1116M–SEEPR–05/05

Figure 8. Byte Write

Figure 9. Page Write

AT24C512

Figure 10. Current Address Read

Figure 11. Random Read

1116M–SEEPR–05/05

11

Figure 12. Sequential Read

12

AT24C512

1116M–SEEPR–05/05

AT24C512

Ordering Information

(1)

Ordering Code Package Operation Range

AT24C512C1-10CI-2.7
AT24C512-10PI-2.7
AT24C512W-10SI-2.7
AT24C512N-10SI-2.7
AT24C512-10TI-2.7

AT24C512C1-10CI-1.8
AT24C512-10PI-1.8
AT24C512W-10SI-1.8
AT24C512N-10SI-1.8
AT24C512-10TI-1.8

AT24C512C1-10CU-2.7
AT24C512C1-10CU-1.8
AT24C512-10PU-2.7
AT24C512-10PU-1.8

(2)

(2)

AT24C512W-10SU-2.7
AT24C512W-10SU-1.8
AT24C512N-10SU-2.7
AT24C512N-10SU-1.8
AT24C512-10TU-2.7
AT24C512-10TU-1.8

(2)

(2)

AT24C512Y4-10YU-1.8
AT24C512U4-10UU-1.8

AT24C512-W2.7-11
AT24C512-W1.8-11

(3)

(3)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

8CN1

8P3
8S2
8S1
8A2

8CN1

8P3
8S2
8S1
8A2

8CN1
8CN1

8P3
8P3
8S2
8S2
8S1
8S1
8A2
8A2
8Y4

8U4-1

Die Sale
Die Sale

Industrial Temperature

(–40°C to 85°C)

Industrial Temperature

(–40°C to 85°C)

Lead-free/Halogen-free/

Industrial Temperature

(–40°C to 85°C)

Industrial Temperature

(–40°C to 85°C)

Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.

2. “U” designates Green package + RoHS compliant.

3. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contact

Serial EEPROM marketing.

Package Type

8CN1 8-lead, 0.300" Wide, Leadless Array Package (LAP)

8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)

8S2 8-lead, 0.200” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)

8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

8Y4 8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP)

8U4-1 8-ball, die Ball Grid Array Package (dBGA2)

Options

–2.7 Low-voltage (2.7V to 5.5V)

–1.8 Low-voltage (1.8V to 3.6V)

1116M–SEEPR–05/05

13

Packaging Information

8U4-1 — dBGA2

A1 BALL PAD CORNER

D

5.

b

E

A1

TOP VIEW

A1 BALL PAD CORNER

1

2

A

e

(e1)

B

C

D

SIDE VIEW

A2

A

d

(d1)

BOTTOM VIEW

8 SOLDER BALLS

5. Dimension 'b' is measured at the maximum solder ball diameter.

This drawing is for general information only.

1150 E. Cheyenne Mtn. Blvd.

R

Colorado Springs, CO 80906

TITLE

8U4-1, 8-ball, 2.47 x 4.07 mm Body, 0.75 mm pitch,
Small Die Ball Grid Array Package (dBGA2)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

NOM

A 0.81 0.91 1.00
A

1

0.15 0.20 0.25

A

2

0.40 0.45 0.50
b 0.25 0.30 0.35
D 2.47 BSC
E 4.07 BSC

e
e1

0.75 BSC

0.74 REF
d 0.75 BSC

d1

0.80 REF

DRAWING NO.

PO8U4-1

MAX

NOTE

1/5/05

REV.

A

14

AT24C512

1116M–SEEPR–05/05

8CN1 – LAP

AT24C512

Marked Pin1 Indentifier

E

A

D

A1

Top View

0.10 mm
TYP

8

e

7

6

5

e1

L1

Bottom View

Note: 1. Metal Pad Dimensions.

2. All exposed metal area shall have the following finished platings.
Ni: 0.0005 to 0.015 mm
Au: 0.0005 to 0.001 mm

1150 E.Cheyenne Mtn Blvd.
Colorado Springs, CO 80906

R

TITLE

8CN1, 8-lead (8 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,

Leadless Array Package (LAP)

Side View

Pin1 Corner

1

COMMON DIMENSIONS

2

SYMBOL

3

b

4

L

A 0.94 1.04 1.14

A1 0.30 0.34 0.38

b 0.36 0.41 0.46 1

D 7.90 8.00 8.10

E 4.90 5.00 5.10

e 1.27 BSC

e1 0.60 REF

L 0.62 .0.67 0.72 1

L1 0.92 0.97 1.02 1

(Unit of Measure = mm)

MIN

NOM

MAX

DRAWING NO.

8CN1

NOTE

11/8/04

REV.

B

1116M–SEEPR–05/05

15

8P3 – PDIP

D1

b3

4 PLCS

Top View

D

e

Side View

N

1

b

b2

A2 A

E

E1

c

eA

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

SYMBOL

A

A2 0.115 0.130 0.195

b 0.014 0.018 0.022 5

b2 0.045 0.060 0.070 6

b3 0.030 0.039 0.045 6

c 0.008 0.010 0.014

D 0.355 0.365 0.400 3

L

D1 0.005

E 0.300 0.310 0.325 4

E1 0.240 0.250 0.280 3

e 0.100 BSC

eA 0.300 BSC 4

L 0.115 0.130 0.150 2

MIN

NOM

–

MAX

–

0.210 2

–

–

3

NOTE

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicu

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

TITLE

16

2325 Orchard Parkway

R

San Jose, CA 95131

AT24C512

8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)

lar to datum.

DRAWING NO.

8P3

01/09/02

REV.

B

1116M–SEEPR–05/05

8S2 – EIAJ SOIC

AT24C512

C

1

Top View

E

N

∅

E1

L

End View

e

D

Side View

b

A

SYMBOL

A1

A 1.70 2.16

A1 0.05 0.25

b 0.35 0.48 5

C 0.15 0.35 5

D 5.13 5.35

E1 5.18 5.40 2, 3

E 7.70 8.26

L 0.51 0.85

∅

e 1.27 BSC 4

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

0° 8°

NOM

MAX

NOTE

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs are not included.

3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.

4. Determines the true geometric position.

5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer sha

2325 Orchard Parkway

R

San Jose, CA 95131

1116M–SEEPR–05/05

TITLE

8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)

ll be 0.010 +0.010/−0.005 mm.

DRAWING NO.

8S2

10/7/03

REV.

C

17

8S1 – JEDEC SOIC

C

1

E

N

∅

E1

L

Top View

End View

e

D

Side View

B

A

SYMBOL

A1

A 1.35 – 1.75

A1 0.10 – 0.25

B 0.31 – 0.51

C 0.17 – 0.25

D 4.80 – 5.00

E1 3.81 – 3.99

E 5.79 – 6.20

e 1.27 BSC

L 0.40 – 1.27

∅ 0° – 8°

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

NOM

MAX

NOTE

18

Note:

These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906

R

TITLE

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)

AT24C512

DRAWING NO.

8S1 B

1116M–SEEPR–05/05

10/7/03

REV.

8A2 – TSSOP

Pin 1 indicator

this corner

AT24C512

123

N

Top View

b

e

D

Side View

A2

E1

E

L1

L

End View

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A

D 2.90 3.00 3.10 2, 5

E 6.40 BSC

E1 4.30 4.40 4.50 3, 5

A – – 1.20

A2 0.80 1.00 1.05

b 0.19 – 0.30 4

e 0.65 BSC

L 0.45 0.60 0.75

L1 1.00 REF

MIN

NOM

MAX

NOTE

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,

1116M–SEEPR–05/05

datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

2325 Orchard Parkway

R

San Jose, CA 95131

TITLE

8A2, 8-lead, 4.4 mm Body, Plastic

Thin Shrink Small Outline Package (TSSOP)

DRAWING NO.

8A2

5/30/02

REV.

B

19

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1116M–SEEPR–05/05