ATMEL AT24C512 User Manual

Features

• Low-voltage and Standard-voltage Operation

– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (V

= 1.8V to 3.6V)

CC

• Internally Organized 65,536 x 8

• Two-wire Serial Interface

• Schmitt Triggers, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility

• Write Protect Pin for Hardware and Software Data Protection

• 128-byte Page Write Mode (Partial Page Writes Allowed)

• Self-timed Write Cycle (5 ms Max)

• High Reliability

– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years

• Automotive Grade, Extended Temperature and Lead-free/Halogen-free

Devices Available

• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP,

8-lead LAP, 8-lead SAP and 8-ball dBGA2 Packages

• Die Sales: Wafer Form, Waffle Pack and Bumped Die

Description

The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s
cascadable feature allows up to four devices to share a common two-wire bus. The
device is optimized for use in many industrial and commercial applications where low­power and low-voltage operation are essential. The devices are available in space­saving 8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead
Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is avail­able in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Two-wire Serial
EEPROM

512K (65,536 x 8)

AT24C512

Table 1. Pin Configurations

Pin Name Function

A0–A1 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

8-ball dBGA2

1

8

VCC

7

WP

6

SCL

5

SDA

Bottom View

A0

2

A1

3

NC

4

GND

8-lead TSSOP

8
7
6
5

A0
A1

NC

GND

VCC
WP
SCL
SDA

A0
A1

NC

GND

1
2
3
4

8-lead Leadless Array

VCC

WP

SCL

SDA

8
7
6
5

A0

1

A1

2

NC

3

GND

4

Bottom View

GND

8-lead SOIC

1
2
3
4

8
7
6
5

VCC

SCL

SDA

8-lead PDIP

1

A0

2

A1

3

NC

4

VCC
WP
SCL
SDA

8-lead SAP

8

WP

7
6
5

Bottom View

8

VCC

7

WP

6

SCL

5

SDA

A0

1

A1

2

NC

3

GND

4

Rev. 1116M–SEEPR–05/05

1

Absolute Maximum Ratings*

Operating Temperature..................................–55°C to +125°C

Storage Temperature .....................................–65°C to +150°C

Voltage on Any Pin

with Respect to Ground ....................................–1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Figure 1. Block Diagram

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

2

AT24C512

1116M–SEEPR–05/05

AT24C512

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.

DEVICE/ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are
hardwired or left not connected for hardware compatibility with other AT24Cxx devices.
When the pins are hardwired, as many as four 512K devices may be addressed on a
single bus system (device addressing is discussed in detail under the Device Address-
ing section. If the pins are left floating, the A1 and A0 pins will be internally pulled down
to GND if the capacitive coupling to the circuit board V
>3 pF, Atmel recommends connecting the address pins to GND.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor­mal write operations. When WP is connected high to V
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND if the capacitive coupling to the circuit board V
>3 pF, Atmel recommends connecting the pin to GND. Switching WP to V
write operation creates a software write protect function.

plane is <3 pF. If coupling is

CC

, all write operations to the

CC

plane is <3 pF. If coupling is

CC

prior to a

CC

Memory Organization AT24C512, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of

128-bytes each. Random word addressing requires a 16-bit data word address.

1116M–SEEPR–05/05

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Table 2. Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V

Symbol Test Condition Max Units Conditions

C

I/O

C

IN

Input/Output Capacitance (SDA) 8 pF V

Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V

I/O

= 0V

Note: 1. This parameter is characterized and is not 100% tested.

Table 3. DC Characteristics
Applicable over recommended operating range from: T
V

= +1.8V to +5.5V (unless otherwise noted)

CC

Symbol Parameter Test Condition Min Typ Max Units

V

CC1

V

CC2

V

CC3

I

CC1

I

CC2

I

SB1

I

SB2

I

SB3

I

LI

I

LO

V

IL

V

IH

V

OL2

V

OL1

Note: 1. V

Supply Voltage 1.8 3.6 V

Supply Voltage 2.7 5.5 V

Supply Voltage 4.5 5.5 V

Supply Current VCC = 5.0V READ at 400 kHz 1.0 2.0 mA

Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA

= 1.8V

V

Standby Current
(1.8V option)

Standby Current
(2.7V option)

Standby Current
(5.0V option)

Input Leakage Current VIN = V

Output Leakage
Current

Input Low Level

Input High Level

(1)

(1)

CC

= 3.6V 3.0

V

CC

= 2.7V

V

CC

= 5.5V 6.0

V

CC

= 4.5 - 5.5V VIN = VCC or V

V

CC

CC or VSS

= V

V

OUT

CC or VSS

Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V

Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

min and VIH max are reference only and are not tested.

IL

= –40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,

AI

1.0 µA

= VCC or V

V

IN

SS

2.0 µA

VIN = VCC or V

SS

SS

6.0 µA

0.10 3.0 µA

0.05 3.0 µA

–0.6 VCC x 0.3 V

VCC x 0.7 VCC + 0.5 V

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AT24C512

1116M–SEEPR–05/05

Table 4. AC Characteristics
Applicable over recommended operating range from T
erwise noted) Test conditions are listed in Note 2.

Symbol Parameter

f

SCL

t

LOW

t

HIGH

t

AA

t

BUF

t

HD.STA

t

SU.STA

t

HD.DAT

t

SU.DAT

t

R

t

F

t

SU.STO

t

DH

t

WR

Endurance

Clock Frequency, SCL 100 400 1000 kHz

Clock Pulse Width Low 4.7 1.3 0.4 µs

Clock Pulse Width High 4.0 1.0 0.4 µs

Clock Low to Data Out Valid 0.1 4.5 0.05 0.9 0.05 0.55 µs

Time the bus must be free before a
new transmission can start

(1)

Start Hold Time 4.0 0.6 0.25 µs

Start Set-up Time 4.7 0.6 0.25 µs

Data In Hold Time 0 0 0 µs

Data In Set-up Time 200 100 100 ns

Inputs Rise Time

Inputs Fall Time

(1)

(1)

Stop Set-up Time 4.7 0.6 0.25 µs

Data Out Hold Time 100 50 50 ns

Write Cycle Time 20 or 5

(1)

5.0V, 25°C, Page Mode 100K 100K 100K Write Cycles

AT24C512

= –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-

A

1.8 Volt 2.7 Volt 5.0 Volt

UnitsMin Max Min Max Min Max

4.7 1.3 0.5 µs

1.0 0.3 0.3 µs

300 300 100 ns

(3)

10 or 5

(3)

10 or 5

(3)

ms

Notes: 1. This parameter is characterized and is not 100% tested.

2. AC measurement conditions:
(connects to VCC): 1.3 kΩ (2.7V, 5V), 10 kΩ (1.8V)

R

L

Input pulse voltages: 0.3VCC to 0.7V

CC

Input rise and fall times: ≤50 ns
Input and output timing reference voltages: 0.5V

CC

3. The Write Cycle Time of 5 ms only applies to the AT24C512 devices bearing the process letter “A” on the package (the mark

is located in the lower right corner on the top side of the package).

1116M–SEEPR–05/05

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Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-

nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 8).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 8).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.

STANDBY MODE: The AT24C512 features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two­wire part can be reset by following these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.

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AT24C512

1116M–SEEPR–05/05