Features
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A0
A1
NC
NC
NC
NC
NC
NC
NC
GND
VCC
WP
NC
NC
NC
NC
NC
NC
SCL
SDA
• Low-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (V
= 2.7V to 5.5V)
CC
– 1.8 (VCC = 1.8V to 3.6V)
• Internally Organized 65,536 x 8
• 2-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 128-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Typical)
• High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
– ESD Protection: >4000V
• Automotive Grade and Extended Temperature Devices Available
• 8-pin PDIP and 20-pin JEDEC SOIC, 8-pin LAP, and 8-ball dBGA
TM
Packages
Description
The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s
cascadable feature allows up to 4 devices to share a common 2-wire bus. The device
is optimized for use in many industrial and commercial applications where low-power
and low-voltage operation are essential. The devices are available in space-saving
8-pin PDIP, 20-pin JEDEC SOIC, 8-pin Leadless Array (LAP), and 8-ball dBGA
ages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to
5.5V) and 1.8V (1.8V to 3.6V) versions.
pack-
2-wire Serial
EEPROM
512K (65,536 x 8)
AT24C512
Pin Configurations
Pin Name Function
A0 - A1 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
20-pin SOIC
8-pin PDIP
A0
A1
NC
GND
1
2
3
4
8
7
6
5
8-pin Leadless Array
VCC
WP
SCL
SDA
8
7
6
5
A0
1
A1
2
NC
3
GND
4
Bottom View
8-ball dBGA
VCC
WP
SCL
SDA
8
7
6
5
A0
2
A1
3
NC
4
GND
1
Bottom View
VCC
WP
SCL
SDA
Rev. 1116D–07/00
1
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0
pins are device address inputs that are hardwired or left not
connected for hardware compatibility with AT24C128/256.
When the pins are hardwired, as many as four 512K
devices may be addressed on a single bus system (device
addressing is discussed in detail under the Device
Addressing section). When the pins are not hardwired, the
default A1 and A0 are zero.
2
AT24C512
WRITE PROTECT (WP): The write protect input, when tied
to GND, allows normal write operations. When WP is tied
high to V
ited. If left unconnected, WP is internally pulled down to
GND. Switching WP to V
ates a software write protect function.
, all write operations to the memory are inhib-
CC
prior to a write operation cre-
CC
Memory Organization
AT24C512, 512K SERIAL EEPROM: The 512K is inter-
nally organized as 512 pages of 128-bytes each. Random
word addressing requires a 16-bit data word address.
AT24C512
Pin Capacitance
(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol Test Condition Max Units Conditions
C
I/O
C
IN
Input/Output Capacitance (SDA) 8 pF V
I/O
= 0V
Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: T
= +1.8V to +5.5V (unless otherwise noted).
V
CC
Symbol Parameter Test Condition Min Typ Max Units
V
V
V
I
I
I
CC1
CC2
CC3
CC1
CC2
SB1
Supply Voltage 1.8 3.6 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC = 5.0V READ at 400 kHz 1.0 2.0 mA
Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA
V
= 1.8V
Standby Current
(1.8V option)
CC
VCC = 3.6V 2.0
= -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
AI
0.2 µA
= VCC or V
V
IN
SS
I
SB2
I
SB3
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note: 1. V
= 2.7V
V
Standby Current
(2.7V option)
Standby Current
(5.0V option)
CC
V
= 5.5V 6.0
CC
= 4.5 - 5.5V VIN = VCC or V
V
CC
Input Leakage Current VIN = V
Output Leakage
Current
Input Low Level
Input High Level
(1)
(1)
V
= V
OUT
CC or VSS
CC or VSS
= VCC or V
V
IN
SS
SS
0.10 3.0 µA
0.05 3.0 µA
-0.6 VCC x 0.3 V
VCC x 0.7 VCC + 0.5 V
0.6 µA
6.0 µA
Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
min and VIH max are reference only and are not tested.
IL
3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.
1.8-volt 2.7-volt 5.0-volt
Symbol Parameter
f
SCL
t
LOW
t
HIGH
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
Clock Frequency, SCL 100 400 1000 kHz
Clock Pulse Width Low 4.7 1.3 0.6 µs
Clock Pulse Width High 4.0 1.0 0.4 µs
Clock Low to Data Out Valid 0.1 4.5 0.05 0.9 0.05 0.55 µs
Time the bus must be free before a new
transmission can start
(1)
Start Hold Time 4.0 0.6 0.25 µs
Start Set-up Time 4.7 0.6 0.25 µs
Data In Hold Time 0 0 0 µs
Data In Set-up Time 200 100 100 ns
Inputs Rise Time
Inputs Fall Time
(1)
(1)
Stop Set-up Time 4.7 0.6 0.25 µs
Data Out Hold Time 100 50 50 ns
Write Cycle Time 20 10 10 ms
(1)
5.0V, 25°C, Page Mode 100K 100K 100K Write Cycles
Notes: 1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
R
(connects to VCC): 1.3KΩ (2.7V, 5V), 10KΩ (1.8V)
L
Input pulse voltages: 0.3V
to 0.7V
CC
CC
Input rise and fall times: ≤50ns
Input and output timing reference voltages: 0.5V
CC
UnitsMin Max Min Max Min Max
4.7 1.3 0.5 µs
1.0 0.3 0.3 µs
300 300 100 ns
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as defined
below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing diagram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
4
AT24C512
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C512 features a low power
standby mode which is enabled: a) upon power-up and b)
after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle
while SCL is high and then (c) create a start condition as
SDA is high.