Atmel AT24C256B Datasheet

Features

• Low-voltage and Standard-voltage Operation

– 1.8 (V

• Internally Organized as 32,768 x 8

• Two-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 1 MHz (5.0V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility

• Write Protect Pin for Hardware and Software Data Protection

• 64-byte Page Write Mode (Partial Page Writes Allowed)

• Self-timed Write Cycle (5 ms Max)

• High Reliability

– Endurance: One Million Write Cycles
– Data Retention: 40 Years

• Lead-free/Halogen-free Devices Available

• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC, 8-lead Ultra Thin Small Array

Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages

• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers

= 1.8V to 5.5V)

CC

Two-wire Serial
EEPROM

256K (32,768 x 8)

AT24C256B

Description

The AT24C256B provides 262,144 bits of serial electrically erasable and programma­ble read-only memory (EEPROM) organized as 32,768 words of 8 bits each. The
device’s cascadable feature allows up to eight devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin SAP, 8­lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is available in
a 1.8V (1.8V to 5.5V) version.

Pin Configurations

Pin Name Function

A0–A2 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

GND Ground

GND

A0

A1

A2

VCC

SDA

WP

SCL

8-lead PDIP

1

2

3

4

8-lead dBGA2

8

7

6

5

8-lead SOIC

1

GND

A0

A1

A2

GND

A0

A1

A2

2

3

4

8-lead TSSOP

1

2

3

4

8

VCC

7

WP

6

SCL

5

SDA

1

A0

2

A1

3

A2

4

GND

8

7

6

5

8

VCC

7

WP

6

SCL

5

SDA

Not
Recommended
for New Design

VCC

WP

SCL

SDA

Bottom View

8-lead Ultra Thin SAP

VCC

8

WP

7

SCL

6

SDA

5

Bottom View

1

A0

2

A1

3

A2

4

GND

Rev. 5279C–SEEPR–3/09

1. Absolute Maximum Ratings*

Operating Temperature  55C to +125C

Storage Temperature 65C to +150C

Voltage on Any Pin
with Respect to Ground  1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Figure 1-1. Block Diagram

VCC

GND

WP

SCL

SDA

A
A
A

2

1

0

START

STOP

LOGIC

LOAD

DEVICE

ADDRESS

COMPARATOR

R/W

*NOTICE: Stresses beyond those listed under “Absolute

SERIAL

CONTROL

LOGIC

COMP

LOAD

DATA W OR D

ADDR/COUNTER

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only;
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

EN

H.V. PUMP/TIMING

DATA RECOVERY

INC

EEPROM

X DEC

Y DEC

D

IN

D

OUT

2

AT24C256B

SERIAL MUX

D

/ACK

OUT

LOGIC

5279C–SEEPR–3/09

2. Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM

device and negative-edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open­drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs
that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices.
When the pins are hardwired, as many as eight 256K devices may be addressed on a single bus
system. (Device addressing is discussed in detail under “Device Addressing,” page 9.) A device
is selected when a corresponding hardware and software match is true. If these pins are left
floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capaci­tive coupling that may appear during customer applications, Atmel recommends always
connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends
using 10k or less.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write
operations. When WP is connected directly to Vcc, all write operations to the memory are inhib­ited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to
capacitive coupling that may appear during customer applications, Atmel recommends always
connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends
using 10k or less.

AT24C256B

3. Memory Organization

AT24C256B, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64

bytes each. Random word addressing requires a 15-bit data word address.

Table 3-1. Pin Capacitance
Applicable over recommended operating range from TA=25C, f = 1.0 MHz, VCC= +1.8V

Symbol Test Condition Max Units Conditions

C

I/O

C

IN

Note: 1. This parameter is characterized and is not 100% tested.

Input/Output Capacitance (SDA) 8 pF V

Input Capacitance (A0,A1, SCL) 6 pF VIN=0V

(1)

I/O

=0V

5279C–SEEPR–3/09

3

Table 3-2. DC Characteristics

Applicable over recommended operating range from: T

Symbol Parameter Test Condition Min Typ Max Units

V

CC1

I

CC1

I

CC2

I

SB1

I

LI

I

LO

V

IL

V

IH

V

OL2

V

OL1

Notes: 1. VILmin and VIHmax are reference only and are not tested.

Supply Voltage 1.8 5.5 V

Supply Current VCC= 5.0V READ at 400 kHz 1.0 2.0 mA

Supply Current VCC= 5.0V WRITE at 400 kHz 2.0 3.0 mA

V

= 1.8V

Standby Current
(1.8V option)

Input Leakage
Current V

CC

= 5.0V

Output Leakage
Current V

CC

= 5.0V

Input Low Level

Input High Level

(1)

(1)

CC

= 5.5V 6.0 µA

V

CC

V

IN=VCC

V

OUT=VCC

or V

or V

Output Low Level VCC= 3.0V IOL= 2.1 mA 0.4 V

Output Low Level VCC= 1.8V IOL= 0.15 mA 0.2 V

= 40Cto+85C, VCC= +1.8V to +5.5V (unless otherwise noted)

AI

1.0 µA

SS

SS

V

IN=VCC

or V

SS

0.10 3.0 µA

0.05 3.0 µA

0.6 VCCx 0.3 V

VCCx 0.7 VCC+ 0.5 V

4

AT24C256B

5279C–SEEPR–3/09

Table 3-3. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from T

= 40C to +85C, VCC= +1.8V to +5.5V, CL = 100 pF (unless oth-

AI

erwise noted). Test conditions are listed in Note 2.

AT24C256B

1.8-volt 2.5, 5.0-volt

Symbol Parameter

f

SCL

t

LOW

t

HIGH

t

i

t

AA

t

BUF

t

HD.STA

t

SU.STA

t

HD.DAT

t

SU.DAT

t

R

t

F

t

SU.STO

t

DH

t

WR

Endurance

Clock Frequency, SCL 400 1000 kHz

Clock Pulse Width Low 1.3 0.4 µs

Clock Pulse Width High 0.6 0.4 µs

Noise Suppression Time

(1)

100 50 ns

Clock Low to Data Out Valid 0.05 0.9 0.05 0.55 µs

Time the bus must be free before a
new transmission can start

(1)

1.3 0.5 µs

Start Hold Time 0.6 0.25 µs

Start Set-up Time 0.6 0.25 µs

Data In Hold Time 0 0 µs

Data In Set-up Time 100 100 ns

(1)

(1)

0.3 0.3 µs

300 100 ns

Inputs Rise Time

Inputs Fall Time

Stop Set-up Time 0.6 0.25 µs

Data Out Hold Time 50 50 ns

Write Cycle Time 5 5 ms

(1)

25°C, Page Mode, 3.3V 1,000,000

Notes: 1. This parameter is ensured by characterization and is not 100% tested.

2. AC measurement conditions:
(connects to VCC): 1.3 k (2.5V, 5.5V), 10 k (1.8V)

R

L

Input pulse voltages: 0.3 V

CC

to 0.7 V

CC

Input rise and fall times:  50 ns
Input and output timing reference voltages: 0.5 V

CC

UnitsMin Max Min Max

Write

Cycles

5279C–SEEPR–3/09

5

4. Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.

Data on the SDA pin may change only during SCL low time periods (see Figure 4-1). Data
changes during SCL high periods will indicate a start or stop condition as defined below.

Figure 4-1. Data Validity

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must

precede any other command (see Figure 4-2).

Figure 4-2. Start and Stop Definition

SDA

SCL

DATA STABLE DATA STABLE

DATA

CHANGE

SDA

SCL

START STOP

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-

ure 4-2).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a “0” during the ninth clock cycle to acknowledge
that it has received each word.

STANDBY MODE: The AT24C256B features a low-power standby mode that is enabled upon
power-up and after the receipt of the stop bit and the completion of any internal operations.

6

AT24C256B

5279C–SEEPR–3/09

SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9
cycles, (c) create another start bit followed by stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.

Figure 4-3. Software Reset

Start bit

AT24C256B

Stop bitStart bitDummy Clock Cycles

SCL

SDA

Figure 4-4. Bus Timing

SCL

t

SU.STA

SDA IN

SDA OUT

123 89

t

HIGH

t

LOW

t

HD.DAT

t

AA

t

SU.DAT

t

DH

t

HD.STA

t

F

t

LOW

t

R

t

SU.STO

t

BUF

Figure 4-5. Write Cycle Timing

SCL

DA

8th BIT

WORDn

Note: 1. The write cycle time tWRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

5279C–SEEPR–3/09

ACK

STOP

CONDITION

(1)

t

wr

START

CONDITION

7

Figure 4-6. Output Acknowledge

SCL

DATA IN

DATA OUT

1

START ACKNOWLEDGE

8

9

8

AT24C256B

5279C–SEEPR–3/09