ATMEL AT24C164-10PI-1.8, AT24C164-10PI, AT24C164-10PC-2.7, AT24C164-10PC-2.5, AT24C164-10PC-1.8 Datasheet

Features

•

Low Voltage and Standard Voltage Operation

– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)

•

Internally Organized 2048 x 8 (16K)

•

2-Wire Serial Interface

•

Schmitt Trigger, Filtered Inputs for Noise Suppression

•

Bidirectional Data Transfer Protocol

•

100 KHz (1.8V, 2.5V, 2.7V) and 400 KHz (5V) Compatibility

•

Write Protect Pin for Hardware Data Protection

•

Cascadable Feature Allows for Extended Densities

•

16-Byte Page Wri te Mode

•

Partial Page Writes Are Allowed

•

Self-Timed Write Cycle (10 ms max)

•

High Reliability

– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >3,000V

•

Automotive Grade and Extended Temperature Devices Available

•

8-Pin JEDEC SOIC and 8-Pin PDIP Packages

Description

The AT24C164 provides 16,38 4 bits of serial electricall y erasable and programma ble
read only memory (EEPROM) organized as 2048 words of 8 bits each. The device’s
cascadable feature allows up to eight devices to share a common 2-wire bus. The
device is optimiz ed for use in ma ny in dustria l and co mmerci al app lica tions where low
power and low voltage operation are essential. The AT24C164 is available in space
saving 8-pin PDIP and 8-pin SOIC packages and is accessed via a 2-wire serial inter­face. In addition, this device is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V),

2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

2-Wire Serial
EEPROM

16K (2048 x 8)

AT24C164

Pin Configurations

Pin Name Function

A0 to A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect

8-Pin PDIP

A0
A1
A2

GND

1
2
3
4

8
7
6
5

VCC
WP
SCL
SDA

A0
A1
A2

GND

8-Pin SOIC

1
2
3
4

2-Wire, 16K
Serial EEPROM

VCC

8

WP

7

SCL

6

SDA

5

Rev. 0105D–07/98

1

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximum Operating Voltage........................................... 6.25V

DC Output Current........................................................5.0 mA

Block Diagram

WP

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the dev ice . This is a s tress rating only an d
functional oper ation of the device at these or an y
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect de vice
reliability .

Pin Description

SERIAL CLOCK (SCL):

edge clock data into each EEPROM device and negative
edge clock data out of each device.

SERIAL DATA (SDA ):

serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.

DEVICE SELECT (A2, A1, A0):

are device address inputs that may be hardwired or actively
driven to V

2

or VSS. These inputs allow the sel ection for

DD

The SCL input is used to positive

The SDA pin is bidirectional for

The A2, A1 and A0 pins

AT24C164

one of eight possible devices sharing a common bus. The
AT24C164 can be made compatible with the AT24C16 by
tying A2, A1 and A0 to V
in detail in the device addressing section.

WRITE PROTECT (WP):

low to GND, allows normal write operations.

. Device addressing is discussed

SS

The write protect input, when tied

Memory Organization

The AT24C164 is internally organized with 256 pages of
8 bytes each. Random word addressing requires an 11 bit
data word address.

AT24C164

Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.

Symbol T est Conditi on Max Units Conditions

C

I/O

C

IN

Input/Output Capacitance (SDA) 8 pF V

I/O

= 0V

Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

Note: 1. This parameter is characterized and is not 100% tested.

DC Characteristics

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,

= +1.8V to +5.5V (unless otherwise noted).

V

CC

Symbol Parameter Test Condition Min Typ Max Units

V

CC1

V

CC2

V

CC3

V

CC4

I

CC

I

CC

I

SB1

I

SB2

I

SB3

I

SB4

I

LI

I

LO

V

IL

V

IH

V

OL2

V

OL1

Note: 1. V

Supply Voltage 1.8 5.5 V
Supply Voltage 2.5 5.5 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Standby Current VCC = 5.0V READ at 100 KHz 0.4 1.0 mA
Standby Current VCC = 5.0V WRITE at 100 KHz 2.0 3.0 mA
Standby Current VCC = 1.8V VIN = VCC or V
Standby Current VCC = 2.5V VIN = VCC or V
Standby Current VCC = 2.7V VIN = VCC or V
Standby Current VCC = 5.0V VIN = VCC or V
Input Leakage Current VIN = VCC or V
Output Leakage Current V
Input Low Level
Input High Level

(1)

(1)

OUT = VCC

or V

SS

SS

SS

SS

SS

SS

-0.6 VCC x 0.3 V

VCC x 0.7 VCC + 0.5 V

0.6 3.0

1.4 4.0

1.6 4.0

8.0 18.0

0.10 3.0

0.05 3.0

Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

min and VIH max are reference only and are not tested.

IL

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

3

AC Characteristics

Applicable over recomme nded operating r ange from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).

2.7-, 2.5-, 1.8-volt 5.0-volt

Symbol Parameter

f

SCL

t

LOW

t

HIGH

t

I

t

AA

t

BUF

t

HD.STA

t

SU.STA

t

HD.DAT

t

SU.DAT

t

R

t

F

t

SU.STO

t

DH

t

WR

Endurance

Notes: 1. This parameter is characterized and is not 100% tested.

(1)

Clock Frequency, SCL 100 400 KHz
Clock Pulse Width Low 4.7 1.2
Clock Pulse Width High 4.0 0.6
Noise Suppression Time
Clock Low to Data Out Valid 0.1 4.5 0.1 0.9
Time the bus must be free before a new

transmission can start
Start Hold Time 4.0 0.6
Start Set-up Time 4.7 0.6
Data In Hold Time 0 0
Data In Set-up Time 200 100 ns
Inputs Rise Time
Inputs Fall Time
Stop Set-up Time 4.7 0.6
Data Out Hold Time 100 50 ns
Write Cycle Time 10 10 ms

5.0V, 25°C, Page Mode 1M 1M Write

(1)

(1)

(1)

(1)

100 50 ns

4.7 1.2

1.0 0.3

300 300 ns

UnitsMin Max Min Max

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

cycles

Device Operation

CLOCK and DATA TRANSITIONS:

mally pulled high wi th an ex ter na l dev ic e. Dat a o n t he SDA
pin may chan ge o nly duri ng S CL l ow t ime per iods (refe r t o
Data Validity timing diagram). Data changes during S CL
high periods will indicate a start or stop condition as
defined below.

START CONDITION:

A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia­gram).

STOP CONDITION:

A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will pla ce the EEPR OM in a standb y power
mode (refer to Start and Stop Definition timing diagram).

4

AT24C164

The SDA pin is nor-

ACKNOWLEDGE:

All addresses and data words are seri­ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock
cycle.

STANDBY MODE:

The AT24C164 features a low power
standby mode which is enabled: a) upon power-up and b)
after the receipt of the STOP bit and the completi on of any
internal operations.

MEMORY RESET:

After an interruption in protocol, power
loss or system reset, the AT24C164 can be reset by follow­ing these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle
while SCL is high and then (c) create a start condition as
SDA is high.