Atmel AT24C08, AT24C16 Schematics

Features

• Medium-voltage and Standard-voltage Operation

– 5.0 (V – 2.7 (V

• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),

1024 x 8 (8K) or 2048 x 8 (16K)

• Two-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bi-directional Data Transfer Protocol

• 100 kHz (2.7V) and 400 kHz (5V) Compatibility

• Write Protect Pin for Hardware Data Protection

• 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes

• Partial Page Writes are Allowed

• Self-timed Write Cycle (5 ms max)

• High-reliability

– Endurance: 1 Million Write Cycles – Data Retention: 100 Years

• 8-lead PDIP and 8-lead JEDEC SOIC Packages

= 4.5V to 5.5V)

= 2.7V to 5.5V)

Two-wire Automotive Serial EEPROM

1K (128 x 8)

Description

The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential. The AT24C01A/02/04/08/16 is available in space-saving 8-lead PDIP and 8-lead JEDEC SOIC packages and is accessed via a two-wire serial interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V) and 2.7V (2.7V to 5.5V) versions.

Table 1. Pin Configuration

Pin Name Function

A0 - A2 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

GND

8-lead PDIP

8-lead SOIC

VCC

SCL

SDA

2K (256 x 8)

4K (512 x 8)

8K (1024 x 8)

16K (2048 x 8)

AT24C01A AT24C02 AT24C04 AT24C08 AT24C16

Note: 1. This device is not recom-

mended for new designs. Please refer to AT24C08A.

2. This device is not recommended for new designs. Please refer to AT24C16A.

(1)

(2)

A0 A1 A2

GND

1 2 3 4

VCC

SCL

SDA

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Absolute Maximum Ratings

Operating Temperature......................................−55°C to +125°C

Storage Temperature .........................................−65°C to +150°C

Voltage on Any Pin

with Respect to Ground........................................ −1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Figure 1. Block Diagram

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or opencollector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).

The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect.

AT24C01A/02/04/08/16

3256F–SEEPR–10/04

AT24C01A/02/04/08/16

The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects.

The AT24C16 does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects.

WRITE PROTECT (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to V write protection feature is enabled and operates as shown see Table 2.

Table 2. Write Protect

WP Pin Status

At V

At GND Normal Read/Write Operations

24C01A 24C02 24C04 24C08

Full (1K) Array

Full (2K) Array

Notes: 1. This device is not recommended for new designs. Please refer to AT24C08A.

2. This device is not recommended for new designs. Please refer to AT24C16A.

Part of the Array Protected

Full (4K) Array

(1)

Normal Read/ Write Operation

24C16

Upper Half (8K) Array

, the

(2)

Memory Organization AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,

the 1K requires a 7-bit data word address for random word addressing.

AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing.

AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing.

AT24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing.

AT24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing.

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Table 3. Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V.

Symbol Test Condition Max Units Conditions

I/O

Input/Output Capacitance (SDA) 8 pF V

I/O

= 0V

Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

Note: 1. This parameter is characterized and is not 100% tested.

Table 4. DC Characteristics Applicable over recommended operating range from: T

= −40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise

noted).

Symbol Parameter Test Condition Min Typ Max Units

CC1

CC2

SB1

SB2

OL2

OL1

Notes: 1. V

Supply Voltage 2.7 5.5 V

Supply Voltage 4.5 5.5 V

Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA

Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA

Standby Current VCC = 2.7V VIN = VCC or V

Standby Current VCC = 5.0V VIN = VCC or V

Input Leakage Current VIN = VCC or V

Output Leakage Current V

Input Low Level

Input High Level

(1)

OUT

= V

or V

−0.6 VCC x 0.3 V

VCC x 0.7 VCC + 0.5 V

1.6 4.0 µA

8.0 18.0 µA

0.10 3.0 µA

0.05 3.0 µA

Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V

Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

min and V

max are reference only and are not tested.

AT24C01A/02/04/08/16

3256F–SEEPR–10/04

Table 5. AC Characteristics Applicable over recommended operating range from T 100 pF (unless otherwise noted).

AT24C01A/02/04/08/16

= −40°C to +125°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and

AT24C01A/02/04/08,

2.7V AT24C16, 2.7V

Symbol Parameter

SCL

LOW

HIGH

BUF

HD.STA

SU.STA

HD.DAT

SU.DAT

SU.STO

Endurance 5.0V, 25°C1M1M1M

Clock Frequency, SCL 400

Clock Pulse Width Low 1.2 1.2 1.2 µs

Clock Pulse Width High 0.6 0.6 0.6 µs

Noise Suppression Time

(2)

Clock Low to Data Out Valid 0.1 0.9 0.1 0.9 0.1 0.9 µs

Time the bus must be free before a new transmission can start

(3)

1.2 1.2 1.2 µs

Start Hold Time 0.6 0.6 0.6 µs

Start Set-up Time 0.6 0.6 0.6 µs

Data In Hold Time 0 0 0 µs

Data In Set-up Time 100 100 100 ns

Inputs Rise Time

Inputs Fall Time

(3)

Stop Set-up Time 0.6 0.6 0.6 µs

Data Out Hold Time 50 50 50 ns

Write Cycle Time 5 5 5 ms

(1)

400 400 kHz

50 50 50 ns

300 300 300 ns

AT24C01A/02/04/08/16,

5.0V

UnitsMin Max Min Max Min Max

Write

Cycles

Notes: 1. The AT24C01A/02/04/08 bearing the process letter “D” on the package (the mark is located in the lower right corner on the

topside of the package), guarantees 400 kHz (2.5V, 2.7V).

2. This parameter is characterized and is not 100% tested (T

= 25°C).

3. This parameter is characterized and is not 100% tested.

Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-

nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 7).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 7).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.

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STANDBY MODE: The AT24C01A/02/04/08/16 features a low-power standby mode

which is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.

Bus Timing

Figure 2. SCL: Serial Clock, SDA: Serial Data I/O

Write Cycle Timing

Figure 3. SCL: Serial Clock, SDA: Serial Data I/O

SCL

SDA

WORDn

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

8th BIT

ACK

STOP

CONDITION

(1)

START

CONDITION

AT24C01A/02/04/08/16

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