ATMEL AT24C256-10PC-1.8, AT24C256-10PC, AT24C256-10CI-2.7, AT24C256-10CI-1.8, AT24C256-10CI Datasheet

1

Features

•

Low Voltage and Standard Voltage Operation

– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)

•

Internally Organized 16,384 x 8 and 32,768 x 8

•

2-Wire Serial Interface

•

Schmitt Trigger, Filtered Inputs for Noise Suppression

•

Bidirectional Data Transfer Protocol

•

1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility

•

Write Protect Pin for Hardware and Software Data Protection

•

64-Byte Page Write Mode (Partial Page Writes Allowed)

•

Self-Timed Write Cycle (5 ms typical)

•

High Reliability

– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
– ESD Protection: > 4000V

•

Automotive Grade and Extended Temperature Devices Available

•

8-Pin JEDEC PDIP, 8-Pin JEDEC and EIAJ SOIC, 14-Pin TSSOP, and
8-Pin Leadless Array Packages

Description

The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and
programmable read onl y mem ory ( EEPROM ) organi zed as 16,384/ 32,768 w ords of 8
bits each. The device’s cascadable feature allows up to 4 devices to share a common
2-wire bus. The device is optimized for use in many industrial and commercial applica­tions where low power and low voltage operation are essential. The devices are avail­able in space-saving 8-pin JEDEC PDIP, 8-pin EIAJ, 8-pin JEDEC SOIC, 14-pin
TSSOP, and 8-pin LAP packages. In addition, the entire family is available in 5.0V
(4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Rev. 0670C–08/98

2-Wire Serial
EEPROMs

128K (16,384 x 8)
256K (32,768 x 8)

AT24C128
AT24C256

Pin Configurations

Pin Name Function

A

0

to A

1

Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect

8-Pin PDIP

1
2
3
4

8
7
6
5

A0
A1

NC

GND

VCC
WP
SCL
SDA

8-Pin SOIC

1
2
3
4

8
7
6
5

A0
A1

NC

GND

VCC
WP
SCL
SDA

8-Pin Leadless Array

Bottom View

1
2
3
4

8
7
6
5

VCC

WP

SCL

SDA

A0
A1
NC
GND

14-Pin TSSOP

1
2
3
4
5
6
7

14
13
12
11
10

9
8

A0

A1
NC
NC
NC
NC

GND

VCC
WP
NC
NC
NC
SCL
SDA

AT24C128/256

2

Absolute Maximum Ratings*

Block Diagram

Pin Description

SERIAL CLOCK (SCL):

The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.

SERIAL DATA (SDA):

The SDA pin is bidirectional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.

DEVICE/PAGE ADDRESSES (A1, A0):

The A1 and A0
pins are device address inputs that are hardwired or left not
connected for hardware compatibility with AT24C32/64.
When the pins are hardwired, as many as four 128K/256K
devices may be addresse d on a sing le bus system (devic e
addressing is discussed in detail under the Device
Addressing section). When the pins are not hardwired, the
default A

1

and A0 are zero.

WRITE PROTECT (WP):

The write protect input, when tied
to GND, allows normal write operations. Wh en WP is tied
high to V

CC

, all write operations to the memory are inhib­ited. If left unconnected, WP is interna lly pulled down to
GND. Switching WP to V

CC

prior to a write oper ation cre-

ates a software write protect function.

Memory Organization

AT24C128/256, 128K/256K SERIAL EEPROM:

The
128K/256K is internal ly organ ized as 25 6/512 pag es of 64­bytes each. Random word addressing requires a 14/15-bit
data word address.

Operating Temperature.................................. -55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the dev ice. This is a stress ratin g only an d
functional oper ati on of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or extende d periods may af fect de vice
reliability.

Storage Temperature.....................................-65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximum Operating Voltage........................................... 6.25V

DC Output Current........................................................5.0 mA

AT24C128/256

3

Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.

Note: This parameter is characterized and is not 100% tested.

DC Characteristics

Applicable over recommended operating range from: T

AI

= -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,

V

CC

= +1.8V to +5.5V (u nless otherwise noted).

Note: VIL min and VIH max are reference only and are not tested

Symbol Test Condition Max Units Conditions

C

I/O

Input/Output Capacitance (SDA) 8 pF V

I/O

= 0V

C

IN

Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V

Symbol Parameter Test Condition Min Typ Max Units

V

CC1

Supply Voltage 1.8 3.6 V

V

CC2

Supply Voltage 2.7 5.5 V

V

CC3

Supply Voltage 4.5 5.5 V

I

CC1

Supply Current VCC = 5.0V READ at 400 kHz 1.0 2.0 mA

I

CC2

Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA

I

SB1

Standby Current
(1.8V option)

V

CC

= 1.8V

V

IN

= VCC or V

SS

0.2

µ

A

V

CC

= 3.6V 2.0

I

SB2

Standby Current
(2.7V option)

V

CC

= 2.7V

V

IN

= VCC or V

SS

0.5

µ

A

VCC = 5.5V 6.0

I

SB3

Standby Current
(5.0V option)

V

CC

= 4.5 - 5.5V VIN = VCC or V

SS

6.0

µ

A

I

LI

Input Leakage Current VIN = V

CC or VSS

0.10 3.0

µ

A

I

LO

Output Leakage Current V

OUT

= V

CC or VSS

0.05 3.0

µ

A

V

IL

Input Low Level

(Note:)

-0.6 VCC x 0.3 V

V

IH

Input High Level

(Note:)

VCC x 0.7 VCC + 0.5 V

V

OL2

Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V

V

OL1

Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

AT24C128/256

4

AC Characteristics

Applicable over recom me nded operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth­erwise noted). Test conditions are listed in Note 2.

Notes: 1. This parameter is characterized and is not 100% tested.

2. AC measurement conditions:
R

L

(connects to VCC): 1.3KΩ (2.7V, 5V), 10KΩ (1.8V)

Input pulse voltages: 0.3V

CC

to 0.7V

CC

Input rise and fall times: ≤50ns
Input and output timing reference voltages: 0.5V

CC

Device Operation

CLOCK and DATA TRANSITIONS:

The SDA pin is nor­mally pulled h ig h w ith an external device . D ata on the SDA
pin may chan ge o nly dur ing SC L lo w ti me p eri ods ( re fer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as defined
below.

START CONDITION:

A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia­gram).

STOP CONDITION:

A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).

ACKNOWLEDGE:

All addresses and data words are seri­ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.

STANDBY MODE:

The AT24C128/256 features a low
power standby mode which is enabled: a) upon power-up
and b) after the rec ei pt of t he S T OP bit a nd th e co mpl eti on
of any internal operations.

MEMORY RESET:

After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow­ing these steps: (a) Clock up to 9 cycles, (b) look for SDA
high in each cycle while SCL is high and then (c) create a
start condition as SDA is high.

Symbol Parameter

1.8-volt 2.7-volt 5.0-volt
Units

MinMaxMinMaxMinMax

f

SCL

Clock Frequency, SCL 100 400 1000 kHz

t

LOW

Clock Pulse Width Low 4.7 1.3 0.6

µ

s

t

HIGH

Clock Pulse Width High 4.0 1.0 0.4

µ

s

t

AA

Clock Low to Data Out Valid 0.1 4.5 0.05 0.9 0.05 0.55

µ

s

t

BUF

Time the bus must be free before a new
transmission can start

(1)

4.7 1.3 0.5

µ

s

t

HD.STA

Start Hold Time 4.0 0.6 0.25

µ

s

t

SU.STA

Start Set-up Time 4.7 0.6 0.25

µ

s

t

HD.DAT

Data In Hold Time 0 0 0

µ

s

t

SU.DAT

Data In Set-up Time 200 100 100 ns

t

R

Inputs Rise Time

(1)

1.0 0.3 0.3

µ

s

t

F

Inputs Fall Time

(1)

300 300 100 ns

t

SU.STO

Stop Set-up Time 4.7 0.6 0.25

µ

s

t

DH

Data Out Hold Time 100 50 50 ns

t

WR

Write Cycle Time 20 10 10 ms

Endurance

(1)

5.0V, 25°C, Page Mode 100K 100K 100K

Write

Cycles

AT24C128/256

5

Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write

cycle.

SCL

SDA

STOP

CONDITION

START

CONDITION

ACK

t

WR

(1)

8th BIT

WORD n