AT24C02A/04A/08A
7
Device Addressing
The 2K, 4K and 8K EEPROM devices all require an 8 bit
device address word following a start condition to enable
the chip for a read or write operation (refer to Figure 1).
The device address word consists of a mandatory one,
zero sequence for th e first four most signifi cant bits as
shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits
for the 2K EEPROM. These 3 bits must compare to their
corresponding hard-wired input pins.
The 4K EEPROM onl y us es th e A 2 and A 1 d ev ic e add ress
bits with the third bit being a memory page address bit. The
two device address bi ts mus t compa re to the ir corr esponding hard-wired input pins. The A0 pin is no connect.
The 8K EEPROM only us es the A 2 devi ce add ress bi t with
the next 2 b its b eing for me mor y page add res sing. The A2
bit must compare to its c or re spon din g h ard- wir ed in put pin .
The A1 and A0 pins are no connect.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will
output a zero. If a compare is not m ade , the chi p wi ll r et urn
to a standby state.
Write Operations
BYTE WRITE:
A write operation requ ires an 8 bit data
word address following the device address word and
acknowledgement. Upon receipt of this a ddress, the
EEPROM will again respond with a zero and then clock in
the first 8 bit data word. Following receipt of the 8 bit data
word, the EEPROM will output a zero and the addr essing
device, such as a m icr oc ontr olle r, mu st term in ate the w rit e
sequence with a stop condition. At this time the
EEPROM
enters an internally-timed write cycle , t
WR
, to the nonvolatile memory. All inputs are disabled during this wr ite cycle
and the EEPROM will not respond until the write is complete (refer to Figure 2).
PAGE WRITE:
The 2K EEPROM is capable of an 8-byte
page write, and the 4K and 8K devices are capable of 16byte page writes.
A page write i s initi ated the same as a byte wri te, but the
microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K)
more data words. The EEPROM will respond with a zero
after each data word received. The mi crocontroller must
terminate the page write sequ ence with a stop cond ition
(refer to Figure 3).
The data word address lower three (2K) or four (4K, 8K)
bits are internally in cr em ente d fo ll owi ng the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page row location. When the
word address, internally generated, reaches the pa ge
boundary, the following byte is pl aced at the beginning of
the same page. If more than ei ght (2 K) or sixt een (4K , 8K)
data words are t ransmi tted to the EEPROM , the dat a word
address will “roll over ” and previous dat a will be overwritten.
ACKNOWLEDGE POLLING:
Once the internally-timed
write cycle has started and the EEPROM inpu ts are disabled, acknowledge polling can be initiated. T his invol ves
sending a start condition followed by the device address
word. The read/write bit is representati ve of the operati on
desired. Only if the internal wri te cycle has c ompleted will
the EEPROM respon d with a zero allowing the read or
write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the
device address word is set to one. There are t hree read
operations: current address read, random address read
and sequential read.
CURRENT ADDRESS REA D:
The internal data word
address counter maintains the last address accessed during the last read or write operation, incremented by one.
This address stays valid between operations as long as the
chip power is maintained. T he address “roll ov er” during
read is from the last byte of the last memory page to the
first byte of the first page. The address “roll over” during
write is from the las t byte of the cur rent page to the first
byte of the same page.
Once the device address with the read/write select b it set
to one is clocked in and acknowledged by the EEPROM,
the current address data word is s erially clo cked out. The
microcontroller does not respond with an input zero but
does generate a following stop condition (refer to Figure 4).
RANDOM READ:
A random read require s a “dummy ” byte
write sequence to load in t he data wo rd addr ess. Once th e
device address word and data word address are clocked in
and acknowledged by the EE PROM, the mi crocontroll er
must generate another start condition. The microcontroller
now initiates a current address read by sending a device
address with the read/write select b it high. The EEP ROM
acknowledges the device address and serially clocks out
the data word. The microcontroller does not respond with a
zero but does generate a following stop condition (refer to
Figure 5).
SEQUENTIAL READ:
Sequential reads are initiated by
either a current address read or a random address read.
After the microcontroller receives a data word, it responds