ATMEL AT24C16N-10SI-2.7, AT24C16N-10SI-2.5, AT24C16N-10SI-1.8, AT24C16N-10SI, AT24C16N-10SC-2.7 Datasheet
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Features
•
Low-Voltage and Standard-Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
•
Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
•
2-Wire Serial Interface
•
Schmitt Trigger, Filtered Inputs for Noise Suppression
•
Bidirectional Data Transfer Protocol
•
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
•
Write Protect Pin for Hardware Data Protection
•
8-Byte Page (1K, 2K), 16-Byte Page (4K, 8K, 16K) Write Modes
•
Partial Page Writes Are Allowed
•
Self-Timed Write Cycle (10 ms max)
•
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >3000V
•
Automotive Grade and Extended Temperature Devices Available
•
8-Pin and 14-Pin JEDEC SOIC, 8-Pin PDIP, 8-Pin MSOP, and 8-Pin TSSOP Packag es
2-Wire
Serial EEPROM
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
Description
The AT24C01A/02/04/08/ 16 prov ides 1024/20 48/4096 /8192/1 6384 bi ts of seria l electrically erasable and programmable read only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low power and low voltage operation are
essential. The AT24C01A /02/04/08/16 is availa ble in sp ace saving 8-pin PDIP ,
(AT24C01A/02/04/08/16), 8-Pin MSOP (AT24001A/02), 8-Pin TSSOP
(AT24C01A/02/04/08/16), and 8-Pin and 14-Pin JEDEC SOIC
(AT24C01A/02/04/08/16) pac kages and is acce ssed via a 2 -wire seri al interface. In
addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V
(2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
A0
A1
A2
GND
A0
A1
A2
GND
A0
A1
A2
GND
8-Pin TSSOP
1
2
3
4
8-Pin MSOP
1
2
3
4
8-Pin SOIC
1
2
3
4
8
VCC
7
WP
6
SCL
5
SDA
8
VCC
7
WP
6
SCL
5
SDA
VCC
8
WP
7
SCL
6
SDA
5
Pin Configurations
Pin Name Function
A0 to A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
14-Pin SOIC
NC
A0
A1
NC
A2
GND
NC
1
2
3
4
5
6
7
14
13
12
11
10
NC
VCC
WP
NC
SCL
9
SDA
8
NC
A0
A1
A2
GND
8-Pin PDIP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
16K (2048 x 8)
AT24C01A
AT24C02
AT24C04
AT24C08
AT24C16
2-Wire, 1K
Serial E
2
PROM
Rev. 0180D–06/98
1
Absolute Maximum Ratings
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage........................................... 6.25V
DC Output Current........................................................5.0 mA
Block Diagram
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the dev ice . This is a s tress rating only an d
functional oper ation of the device at thes e o r any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect de vice
reliability .
Pin Description
SERIAL CLOCK (SCL):
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA):
serial data transfer. This pin is open-drain driv en and may
be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2 , A1, A0):
and A0 pins are device address inputs that are hard wired
for the AT24C01A and the AT24C02. As many as eight
1K/2K devices may be addres sed on a s ingle bus syste m
(device addressing is discussed in detail under the Device
Addressing section) .
The AT24C04 uses the A2 and A1 i nputs for hard wire
addressing and a total of four 4K devices may be
2
AT24C01A/02/04/08/16
The SCL input is used to positive
The SDA pin is bidirectional for
The A2, A1
addressed on a si ngle b us sy s tem . The A0 pi n i s a no c onnect.
The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a
single bus system. The A0 and A1 pins are no connects.
The AT24C16 does not use the dev ice address pin s which
limits the number of devices on a single bus to one. The
A0, A1 and A2 pins are no connects.
WRITE PROTECT (WP):
Write Protect pin that provides hardware data protection.
The Write Protect pin allows normal read/write oper ations
when connected to groun d (GND). Wh en the Write Pr otect
pin is connected to V
enabled and operates as shown in the following table.
The AT24C01A/02/04/16 has a
, the write pr otection fe ature is
CC
AT24C01A/02/04/08/16
WP Pin
Status
At V
At GND Normal Read/Write Operations
24C01A 24 C02 24C04 24C08 24C16
Full (1K)
CC
Array
Part of the Array Protected
Full (2K)
Array
Full (4K)
Array
Normal
Read/
Write
Operation
Upper
Half
(8K)
Array
AT24C02, 2K SERIAL EEPROM:
256 pages of 1-byte ea ch, the 2K requir es an 8-bit data
word address for random word addressing.
AT24C04, 4K SERIAL EEPROM:
organized with 256 pages of 2 byt es each. Random word
addressing AT24C01A/02/04/08/16 requires a 9-bit data
word address.
AT24C08, 8K SERIAL EEPROM:
organized with 4 blocks of 256 pages of 4 bytes each. Ran-
Internally organized wi th
The 4K is interna lly
The 8K is interna lly
dom word addressing requires a 10-bit data word address.
Memory Organization
AT24C01A, 1K SERIAL EEPROM:
with 128 pages of 1- byte e ac h, t he 1 K re qui res a 7 - bit dat a
word address for random word addressing.
Pin Capacitance
(1)
Internally o rganized
AT24C16, 16K SERIAL EEPROM:
The 16K is internally
organized with 8 blocks of 256 pages of 8 bytes each. Random word addressing requires an 11-bit data word
address.
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol Test Condition Max Units Conditions
C
I/O
C
IN
Input/Output Capacitance (SDA) 8 pF V
Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.
I/O
= 0V
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
= +1.8V to +5.5V (unless otherwise noted).
V
CC
Symbol Parameter Test Condition Min Typ Max Units
V
CC1
V
CC2
V
CC3
V
CC4
I
CC
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note: 1. V
Supply Voltage 1.8 5.5 V
Supply Voltage 2.5 5.5 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA
Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA
Standby Current VCC = 1.8V VIN = VCC or V
Standby Current VCC = 2.5V VIN = VCC or V
Standby Current VCC = 2.7V VIN = VCC or V
Standby Current VCC = 5.0V VIN = VCC or V
Input Leakage Current VIN = VCC or V
Output Leakage Current V
Input Low Level
Input High Level
(1)
(1)
OUT
= V
CC
or V
SS
SS
SS
SS
SS
SS
-0.6 VCC x 0.3 V
VCC x 0.7 VCC + 0.5 V
0.6 3.0
1.4 4.0
1.6 4.0
8.0 18.0
0.10 3.0
0.05 3.0
Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
min and V
IL
max are reference only and are not tested.
IH
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
3
AC Characteristics
Applicable over recomme nded operating r ange from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate an d
100pF (unless otherwise noted).
2.7-, 2.5-, 1.8-volt 5.0-volt
Symbol Parameter
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
Note: 1. This parameter is characterized and is not 100% tested.
(1)
Clock Frequency, SCL 100 400 kHz
Clock Pulse Width Low 4.7 1.2
Clock Pulse Width High 4.0 0.6
Noise Suppression Time
Clock Low to Data Out Valid 0.1 4.5 0.1 0.9
Time the bus must be free before
a new transmission can start
Start Hold Time 4.0 0.6
Start Set-up Time 4.7 0.6
Data In Hold Time 0 0
Data In Set-up Time 200 100 ns
Inputs Rise Time
Inputs Fall Time
Stop Set-up Time 4.7 0.6
Data Out Hold Time 100 50 ns
Write Cycle Time 10 10 ms
5.0V, 25°C, Page Mode 1M 1M Write Cycles
(1)
(1)
(1)
(1)
100 50 ns
4.7 1.2
1.0 0.3
300 300 ns
UnitsMin Max Min Max
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
Device Operation
CLOCK and DATA TRANSITIONS:
mally pulled high with an externa l device. Data on the SDA
pin may chan ge o nly duri ng S CL l ow t ime per iods (refe r t o
Data Validity timing diagram). Data changes during S CL
high periods will indicate a start or stop condition as
defined below.
START CONDITION:
A high-to-low transition of SDA wi th
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing diagram).
STOP CONDITION:
A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command wi ll p lace the EEPR OM i n a s tandb y power
mode (refer to Start and Stop Definition timing diagram).
4
AT24C01A/02/04/08/16
The SDA pin i s nor-
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock
cycle.
STANDBY MOD E:
The AT24C01A/02/04/08/16 features a
low power standby mode which is enabled: (a) upon powerup and (b) after the receipt of the STOP bit and the completion of any internal operations.
MEMORY RESET:
After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition as SDA is high.
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle T iming
SCL: Serial Clock, SDA: Serial Data I/O
AT24C01A/02/04/08/16
(1)
t
WR
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
5
Data Validity
Start and Stop Definition
Output Acknowledge
6
AT24C01A/02/04/08/16
AT24C01A/02/04/08/16
Device Addressing
The 1K, 2K, 4K, 8K and 16K EEPROM devices all require
an 8-bit device address word following a start condition to
enable the chip for a read or write operation (refer to Figure
1).
The device address word consists of a mandatory one,
zero sequence for th e first four most sig nificant bits as
shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits
for the 1K/2K EEPROM. T hese 3 bits must compare to
their corresponding hard-wired input pins.
The 4K EEPROM onl y us es the A2 and A1 devic e add ress
bits with the third bit being a memory page address bit. The
two device address bi ts mus t compa re to the ir co rrespo nding hard-wired input pins. The A0 pin is no connect.
The 8K EEPROM only uses the A 2 devi ce add ress bit wit h
the next 2 b its being f or me mor y page a ddres sing. The A2
bit must compare to its cor r esponding hard-wired in put pin .
The A1 and A0 pins are no connect.
The 16K does not use any device address bits but instead
the 3 bits are used for m emory pa ge addressi ng. Thes e
page addressing bits on the 4K, 8K, and 16K devices
should be considered the mo st significa nt bits of the data
word address which follows. The A0, A1 and A2 pins are no
connect.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will
output a zero. If a compare is not m ade , the c hip wi ll r et ur n
to a standby state.
Write Operations
BYTE WRITE:
word address following the device address word and
acknowledgment. U pon receipt of this address, the
EEPROM will again respond with a zero and then clock in
the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a zero and the addr essing
device, such as a mi croc ontr olle r, mus t ter min ate the w rit e
sequence with a stop condition. At this time the EEPROM
enters an internally-timed write cycle, t
memory. All inputs are disabled during this write cycle and
the EEPROM will not respond until the writ e is complete
(refer to Figure 2).
PAGE WRITE:
byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes.
A page write is ini tiated the same as a byte wri te, but the
microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM
A write operation requi res an 8-bit data
, to the nonvolatile
WR
The 1K/2K EEPROM is capable of an 8-
acknowledges receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K, 8K,
16K) more data words . The EEPROM will respond with a
zero after each data word received. The microcontroller
must terminate the p age wri te se quenc e with a s top c ondition (refer to Figure 3).
The data word address lower three (1K/2K) or four (4K, 8K,
16K) bits are intern ally inc remen ted foll owing th e rece ipt of
each data word. The higher data wor d addres s bits ar e not
incremented, retaining the memory page row location.
When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the
EEPROM, the data word address will “roll over” and previous data will be overwritten.
ACKNOWLEDGE POLLING:
write cycle has started and the EEPROM inpu ts are disabled, acknowledge polling can be initia ted. This invol ves
sending a start condition followed by the device address
word. The read/write bit is repres entative of the oper ation
desired. Only if the internal wri te cycle has c ompleted will
the EEPROM respon d with a zero allowing the read or
write sequence to continue.
Once the internally-time d
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the
device address word is set to one. There are t hree read
operations: current address read, random address read
and sequential read.
CURRENT ADDRESS REA D:
address counter maintains the last address accessed during the last read or write operation, incremented by one.
This address stays valid between operations as long as the
chip power is maintained. T he address “roll over” during
read is from the last byte of the last memory page to the
first byte of the first page. The address “roll over” during
write is from the las t byte of the c urrent page to the first
byte of the same page.
Once the device address with the read/wr ite select b it set
to one is clocked in and acknowledged by the EEPROM,
the current address data word is s erially clo cked out. The
microcontroller does not respond with an input zero but
does generate a following stop condition (refer to Figure 4).
RANDOM READ:
write sequence to load i n the data wo rd addr ess. Once th e
device address word and data word address are clocked in
and acknowledge d by the EE PROM, the microcontroll er
must generate another start condition. The microcontroller
now initiates a current address read by sending a device
address with the read/write select b it high. The EEP ROM
acknowledges the device address and serially clocks out
A random read require s a “dummy ” byte
The internal data word
7
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