ATMEL AT24C02A, AT24C04A User Manual
Features
• Write Protect Pin for Hardware Data Protection
– Utilizes Different Array Protection Compared to the AT24C02/04
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 256 x 8 (2K), 512 x 8 (4K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 100 kHz (1.8V) and 400 kHz (2.5V, 2.7V, 5V) Clock Rate
• 8-byte Page (2K), 16-byte Page (4K) Write Modes
• Partial Page Writes Allowed
• Self-timed Write Cycle (5 ms Max)
• High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade, Extended Temperature and Lead-Free/Halogen-Free Devices
Available
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead TSSOP and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers.
Two-wire Serial
EEPROM
2K (256 x 8)
4K (512 x 8)
AT24C02A
Description
The AT24C02A/04A provides 2048/4096 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256/512 words of 8 bits each. The
device is optimized for use in many industrial and commercial applications where lowpower and low-voltage operation are essential. The AT24C02A/04A is available in
space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP packages and is accessed via a two-wire serial interface. In addition, the entire family is
available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
Table 1. Pin Configuration
GND
A0
A1
A2
GND
1
2
3
4
8-lead PDIP
1
A0
2
A1
3
A2
4
8-lead SOIC
1
2
3
4
A0
A1
A2
GND
8
VCC
7
WP
6
SCL
5
SDA
VCC
8
WP
7
SCL
6
SDA
5
Pin Name Function
A0–A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No-connect
8-lead TSSOP
1
A0
2
A1
3
A2
4
GND
8-lead MAP
VCC
8
WP
7
SCL
6
SDA
5
Bottom View
8
VCC
7
WP
6
SCL
5
SDA
A0
1
A1
2
A2
3
GND
4
8-ball dBGA2
VCC
8
WP
7
SCL
6
SDA
5
Bottom View
AT24C04A
Rev. 0976Q–SEEPR–8/05
1
Absolute Maximum Ratings*
Operating Temperature........................................ −40°C to +85°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground ........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
STA RT
STOP
LOGIC
Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device
address inputs that must be hardwired for the AT24C02A. As many as eight 2K devices
may be addressed on a single bus system. (Device addressing is discussed in detail
under Device Addressing, page 8).
2
AT24C02A/04A
0976Q–SEEPR–8/05
AT24C02A/04A
The AT24C04A uses the A2 and A1 inputs for hardwire addressing, and a total of four
4K devices may be addressed on a single bus system. The A0 pin is a no-connect.
WRITE PROTECT (WP): The AT24C02A/04A have a WP pin that provides hardware
data protection. The WP pin allows normal read/write operations when connected to
ground (GND). When the WP pin is connected to V
enabled and operates as shown.
Table 2 . Write Protect
Part of the Array Protected
WP Pin Status
24C02A 24C04A
, the write protection feature is
CC
At V
CC
At GND Normal Read/Write Operations
Upper Half (1K) Array Upper Half (2K) Array
Memory Organization AT24C02A, 2K SERIAL EEPROM: The 2K is internally organized with 32 pages of 8
bytes each. Random word addressing requires an 8-bit data word address.
AT24C04A, 4K SERIAL EEPROM: The 4K is internally organized with 32 pages of 16
bytes each. Random word addressing requires a 9-bit data word address.
Table 3. Pin Capacitance
Applicable over recommended operating range from TAI = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol Test Condition Max Units Conditions
C
I/O
C
IN
Note: 1. This parameter is characterized and is not 100% tested.
Input/Output Capacitance (SDA) 8 pF V
Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V
(1)
I/O
= 0V
0976Q–SEEPR–8/05
3
Table 4. DC Characteristics
Applicable over recommended operating range from: T
= −40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)
AI
Symbol Parameter Test Condition Min Typ Max Units
V
V
V
V
I
I
I
I
I
I
I
I
V
V
V
V
CC1
CC2
CC3
CC4
CC
CC
SB1
SB2
SB3
SB4
LI
LO
IL
IH
OL2
OL1
Supply Voltage 1.8 5.5 V
Supply Voltage 2.5 5.5 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA
Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA
Standby Current VCC = 1.8V VIN = VCC or V
Standby Current VCC = 2.5V VIN = VCC or V
Standby Current VCC = 2.7V VIN = VCC or V
Standby Current VCC = 5.0V VIN = VCC or V
Input Leakage Current VIN = VCC or V
Output Leakage Current V
Input Low Level
Input High Level
(1)
(1)
OUT
= V
CC
or V
SS
SS
SS
SS
SS
SS
−0.6 VCC x 0.3 V
VCC x 0.7 VCC + 0.5 V
0.6 3.0 µA
1.4 4.0 µA
1.6 4.0 µA
8.0 18.0 µA
0.10 3.0 µA
0.05 3.0 µA
Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
Note: 1. VIL min and VIH max are reference only and are not tested.
4
AT24C02A/04A
0976Q–SEEPR–8/05
Table 5. AC Characteristics
Applicable over recommended operating range from T
pF (unless otherwise noted)
Symbol Parameter
AT24C02A/04A
= −40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100
AI
1.8-volt 2.5, 2.7, 5.0-volt
UnitsMin Max Min Max
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
Clock Frequency, SCL 100 400 kHz
Clock Pulse Width Low 4.7 1.2 µs
Clock Pulse Width High 4.0 0.6 µs
Noise Suppression Time
(2)
Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 µs
Time the bus must be free before
a new transmission can start
(1)
4.7 1.2 µs
Start Hold Time 4.0 0.6 µs
Start Set-up Time 4.7 0.6 µs
Data In Hold Time 0 0 µs
Data In Set-up Time 200 100 ns
Inputs Rise Time
Inputs Fall Time
(1)
(1)
Stop Set-up Time 4.7 0.6 µs
Data Out Hold Time 100 50 ns
Write Cycle Time 5 5 ms
(1)
5.0V, 25°C, Page Mode 1M 1M Write Cycles
Note: 1. This parameter is characterized and is not 100% tested.
100 50 ns
1.0 0.3 µs
300 300 ns
0976Q–SEEPR–8/05
5
Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 2). Data changes during SCL high periods will indicate a start or stop condition as
defined below.
Figure 2. Data Validity
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
that must precede any other command (see Figure 3).
Figure 3. Start and Stop Definition
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 3).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words.
received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C02A/04A/08A/16A features a low-power standby mode
that is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any
two-wire part can be reset by following these steps:
1. Clock up to 9 cycles
2. Look for SDA high in each cycle while SCL is high
3. Create a start condition as SDA is high.
6
AT24C02A/04A
.
The EEPROM sends a “0” to acknowledge that it has
0976Q–SEEPR–8/05
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