– Wide Power Supply Range - 3.0V to 5.5V
– Ideal for Battery Powered Systems
•
High Speed Operation
– 20 ns max Propagation Delay at V
•
Commercial and Industrial Temperature Ranges
•
Familiar 22V10 Logic Architecture
•
Low Power 3-Volt CMOS Operation
CC
= 3.0V
AT22LV10LAT22LV10
TempCom./Ind.Com./Ind.
(mA)4 / 535 / 45
I
CC
•
CMOS and TTL Compatible Inputs and Outputs
–10 µA Leakage Maximum
•
Reprogrammable - Tested 100% for Programmability
•
High Reliability CMOS Technology
– 2000V ESD Protection
– 200 mA Latchup Immunity
•
Dual-In-Line and Surface Mount Packages
V
= 3.6V
CC
Logic Diagram
Description
The AT22LV10 and AT22LV10L are low volta ge compat ible CMO S high perfor mance
Programmable Logic Devices (PLDs). Speeds down to 20 ns and po wer dissipation
as low as 14.4 mW ar e offered . All sp eed rang es are spe cifi ed over th e 3.0V to 5. 5V
range. All pins offer a low ±10 µA leakage.
(continued)
Low-Voltage UV
Erasable
Programmable
Logic Device
AT22LV10
AT22LV10L
Pin Configurations
Pin NameFunction
CLK/INClock and Logic Input
INLogic Inputs
I/OBidirectional Buffers
*No Internal Connection
VCC3.0V to 5.5V Supply
DIP/SOICPLCC
Rev. 0190C— 05/98
1
The AT22LV10L provides the optimum low power CMOS
PLD solution, with lo w DC power (1 mA typical at V
CC
=
3.3V) and full CMOS output le ve ls. The AT2 2LV 10L sig ni ficantly reduces total system power, allowing battery powered operation.
Full CMOS output levels help reduce power in many other
system components.
The AT22LV10 and AT22LV10L logic architectures ar e
identical to the familiar 22V10. Each output is allocated
from eight to 16 product terms, which allows highly complex logic functions to be realized.
Two additional product terms are included to provide synchronous preset an d asy nchr onous r eset . These te rms ar e
common to all ten registers. All registers are automatically
cleared upon power up.
Register pr el o ad sim p li fi e s te s ti n g. A secu r i ty fu se pr e v en ts
unauthorized copying of programmed fuse patterns.
Logic Options
Absolute Maximum Ratings*
Temperature Under Bias................................-55°C to +125°C
Storage Temperature .....................................-65°C to +150°C
Voltage on Any Pin with
Respect to Ground........................................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming...................................-2.0V to +14.0V
Programming Voltage with
Respect to Ground......................................-2.0V to +14.0V
*NOTICE:Stresses beyond those listed under “Absolute Maxi-
mum Ratings” ma y cause permanent d amage to th e
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this specif ication is not implie d. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Note:1.Minimum voltage is -0.6V dc whihc may undershoot
to -2.0V for pulses of less than 20 ns. Maximum pin
voltage is V
+ 2.0V for pulses of less than 20 ns.
V
CC
+ 0.75V dc which may unders hoo t to
CC
(1)
(1)
(1)
2
Output Options
DC and AC Operating Conditions
CommercialIndustrial
Operating Temperature (Case)0°C - 70°C-40°C - 85°C
VCC Power Supply3.0V to 5.5V3.0V to 5.5V
The registers in the AT22LV10 and AT22LV10L are provided with circuitry to allow loading of each r egister asy nchronously with either a high or a low. T his feature will
simplify testing since any state can be forced into the registers to control test sequencing. A V
will force the register high ; a V
IL
dent of the p olarity b it (C0) setting. The prel oad stat e is
entered by placing an 11.5V to 13V signal on pin 8 on
level on the I/O pin
IH
will force it low, indep en-
AT22LV10(L)
DIPs, and pin 10 on SMPs. When the clock pin is pulsed
high, the data on the I/O p ins is placed i nto the t en registers.
Level forc ed on registered output
pin during preload cycle
V
IH
V
IL
Register state after
cycle
High
Low
Power-Up Reset
The registers in the AT22LV10 and AT22LV10L are
designed to reset during power up. At a point delayed
slightly from VCC crossing 2.5V, all register s will be res et
to the low state. The output state will depend on the polarity
of the output buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The V
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and
3. The clock must remain stable during t
Pin Capacitance
C
IN
C
OUT
Note:1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
rise must be monotonis;
CC
(f = 1 MHz, T = 25°C)
ParameterDescriptionMinTypMaxUnits
Power-Up
Reset Time
PR
t
PR
.
(1)
TypMaxUnitsConditions
58pFV
68pFV
6001000ns
= 0V
IN
= 0V
OUT
Erasure Characteristics
The entire fuse array of an AT22LV10 or AT22LV10L is
erased after exposure to ult raviolet l ight at a wavelen gth o f
2537 Å. Complete erasure is assured after a minimum of
20 minutes exposur e using 12,00 0
spaced one inch away from the chip. Minimum erase time
for lamps at other intensity ratings can be calculated from
µW/cm
2
intensity lamps
•
the minimum inte grated erasur e dose of 1 5 W
sec/cm2. To
prevent unintentional erasure, an opaque label is recommended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent
indoor lighting or sunligh t.