ATMEL AT17C128A-10JI, AT17C128A-10JC, AT17LV256A-10JI, AT17LV256A-10JC, AT17LV128A-10JI Datasheet

...

Features

•

EE Programmab le 65,536 x 1, 131,0 72 x 1 and 262,1 44 x 1 bit Serial M emories De signed to Store Configuration Programs for Programmable Gate Arrays

•

Simple Interface to SRAM FPGAs Requires Only One User I/O Pin

•

Able to Configure with EPF6000 and EPF8000, Flex 10K FPGAs

•

Cascadable To Support Additional Configurations or Future Higher-Density Arrays (17C128/256 only)

•

Low-Power CMOS EEPROM Process

•

Programmable Reset Polarity

•

Available in Industry-Standard Pin-Compatible PLCC Package

•

In-System Programmable via 2-Wire Bus

•

Emulation of 24CXX Serial EEPROMs

•

Available in 3.3V and 5V Versions

Description

The AT17C65/128/256A and AT17LV65/128/256A (AT17A Series) FPGA Configuration EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17A Series is packaged in the popular 20-pin PLCC. The AT17 A Series family uses a sim ple s erial-ac cess p rovide s to configure one or more FPGA devices. The AT17A Series organization suppli es enough memory t o confi gure one or multipl e smal ler FPGA s. Using a speci al featu re of the AT17A Series, the user can select the polarity of the reset function by programming a special EEPROM bit.

The AT17A Series is pin compatible with the industry standard configurator, and can be programmed with industry standard programmers.

Pin Configurations

20-Pin PLCC

4 5 6 7 8

18 17 16 15 14

CLK (DCLK)

NC NC NC

RESET/OE (RESET/OE)

SER_EN NC NC NC NC

321

910111213

CE (nCS)

GND

CEO (nCASC)

DATANCVCC

Rev. 0996A–07/98

FPGA Configuration EEPROM

65K, 128K and 256K

AT17CxxxA AT17LVxxxA

AT17A Series

Controlling The AT17A Series Serial EEPROMs

Most connections betwe en the FPG A devic e and the s erial EEPROM are simple and self-explanatory.

• The DATA output of the AT17A Se ries drives DIN of the FPGA devices.

• The master FPGA CCLK output dr ives the CLK inpu t of the AT17A Series.

• The CEO

output of any AT17C/LV128/256A drives the

input of the next AT17C/LV65/128/256 in a cascade

chain of PROMs.

•SER_EN

must be connected to VCC.

There are, however, two different ways to use the inputs CE

and OE, as shown in the AC Characteristics wave-

forms.

Condition 1

The simplest connection is to have the FPGA D/P output drive both CE

and RESET/OE in parall el (Fi gur e 1 ). Due to its simplicity, however, this method will fail if the FPGA receives an external rese t cond ition d uring the c onfigur a-

tion cycle. If a system reset is applied to the F PGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the AT17A Series does not s ee the exte rnal reset s ignal and wi ll not reset its internal address co unters and, co nsequently, wil l remain out of sync with the FPGA for the remainder of the configuration cycle.

Condition 2

The FPGA D/P output drives only the CE input of the AT17A Series, wh ile its OE

input is driven by the inve rsion

of the input to the FP G A RES ET

input pin. This conn ec tio n works under all nor mal cir cums ta nce s, ev en when the us er aborts a configuration before D/P

has gone high. A hig h

level on the RESET/OE

input to the AT17C/LVxxxA – during FPGA reset – clears the Configurator's internal address pointer, so that the reconfiguration starts at the beginning. The AT17A Series does not require an inverter since the RESET polarity is programmable.

Block Diagram

AT17A Series

Pin Configurations

PLCC/S

OIC DIP

Pin Pin Name I/O Description

2 1 DATA I/O Three-state DATA output for reading. Input/Output pin for programming. 4 2 CLK I Clock input. Used to increment the internal address and bit counter for reading and

programming.

8 3 RESET/OE RESET/Output Enable input (when SER_EN is High). A low level on both the CE and

RESET/OE

inputs enab les the da ta ou tput driv er. A h igh level on RESET /OE rese ts bo th the address and bit counters. A logic polarity of this input is programmable as either RESET/OE or RESET/OE. This document describes the pin as RESET/OE.

94CE

I Chip Enable input. Used for device selection. A low level on both CE and OE enables the

data output driver. A high level on CE

disables both the address and bit counters and forces te device into a low-power mode. Note this pin will not enable/disable the device in 2-wire serial mode (ie; when SER_EN is low).

10 5 GND Ground pin 12 6 CEO O Chip Enable Out output. This signal is asserted low on the clock cycle following the last

bit read from the memory. It will stay low as long as CE and OE are both low. It will then follow CE

until OE goes high. Thereafter, CEO will stay high until the entire PROM is

read again and senses the status of RESET polarity.

A2 I Device selection input, A2. This is used to enable (or select) the device during

programming and when SER _EN

is low (see Programming Guide for more details).

18 7 SER_EN I Serial enable is normally high during FPGA loading operations. Bringing SER_EN low,

enables the 2-wire serial interface for programming.

20 8 V

+3.3V/+5V power supply pin.

Absolute Maximum Ratings*

Operating Temperature..................................-55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the dev ice. Th is is a s tress rating only an d functional oper ati on of the de vi ce at t hes e o r any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions f or e xtended periods ma y af fect dev ice reliability .

Storage Temperature.....................................-65°C to +150°C

Voltage on Any Pin

with Respect to Ground.............................-0.1V to V

CC +

0.5V

Supply Voltage (V

) .......................................-0.5 V to + 7.0V

Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C

ESD (R

ZAP

= 1.5K, C

ZAP

= 100 pF)................................. 2000V

AT17A Series

FPGA Master Serial Mode Summary

The I/O and logic functions o f the FPGA and their assoc iated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, dependin g on the state of th e three FPGA mode pi ns. In Master M ode, the FPGA automatically loads the configuration program from an external memory. The Serial Configuration EEPROM has been designed for compatibility with the Master Serial Mode.

Cascading Serial Configuration EEPROMs (AT17C/LV256A)

For multiple FPGAs config ured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded Configurators provide additional memory (17C/LV128/256A only).

After the last bit f rom t he first Configurator is rea d, t he next clock signal to the Configurator asserts its CEO

output Low and disables its DA TA line . The sec ond Confi gurator r ecognizes the low lev el o n i ts CE

input and enables i ts DATA

output.

Figure 1.

Condition 1 Connection

After configuration is complete, the address counters of all cascaded Configurators are reset if the reset signal drives the RESET/OE

on each Configurator Active.

If the address counters are not to be reset upon completion, then the RES ET/O E

inputs can be tied to groun d. For more details, please refere nc e the A T17C S er ies Pr o gramming Guide

Programming Mode

The programming mode is entered by bringing SER_E N low. In this mode the chip can be program med by the 2wire interface. The programming is done at V

supply only. Programming super voltages are generated inside the chip. See the Programming Specification for Atmel’s Configuration Memories Application Note for further information. The AT17C Series parts are rea d/write at 5V nominal . The AT17LV parts are read/write at 3.0V nominal.

AT17C/LVxxx Reset Polarity

The AT17C/LVxxxA lets the user choose the reset polarity as either RESET/OE

or RESET/OE.

Standby Mode

The AT17C/LVxxxA enters a low-power standby mode whenever CE

is asserted high. In this mode, the Configurator consumes less than 1.0 mA of current. The output remains in a high-impedance state regardless of the state of the OE

input.

REBOOT

M2 M1 M0

FPGA

CCLK

CON

FLEX DEVICE

SERIAL

EEPROM

DATA CLK

SER_EN

RESET/OE

AT17CXX

FLEX 10K, FLEX 16K (CLK REQUIRED)

Operating Conditions

Symbol Description

AT17Cxxx AT17LVxxx

UnitsMin/Max Min/Max

Commercial Supply voltage relative to GND

-0°C to +70°C

4.75/5.25 3.0/3.6 V

Industrial Supply voltage relative to GND

-40°C to +85C

4.5/5.5 3.0/3.6 V

Military Supply voltage relative to GND

-55°C to +125C

4.5/5.5 3.0/3.6 V

+ 7 hidden pages