ATMEL AT17C256-10PI, AT17C256-10PC, AT17C256-10JI, AT17C256-10JC, AT17C128-10SI Datasheet
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Features
•
E2 Programmable 65,536 x 1, 131,072 x 1, and 262,144 x 1 bit Seria l Memories Design ed
To Store Configuration Programs For Programmable Gate Arrays
•
Simple Interface to SRAM FPGAs Requires Only One User I/O Pin
•
Compatible With AT6000 FPGAs, ATT3000 FPGA, EPF8000 FPGAs, ORCA FPGAs,
XC2000, XC3000, XC4000, XC5000 FPGAs, MPA1000
•
Cascadable To Support Additional Configurations or Future Higher-density Arrays
(17C128 and 17C256 only)
•
Low-power CMOS EEPROM Process
•
Programmable Reset Polarity
•
Available In the Space-efficient Plastic DIP or Surface-mount
PLCC and SOIC Packages
•
In-System Programmable Via 2-Wire Bus
•
Emulation of 24CXX Serial EPROMs
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Available in 3.3V ± 10% LV Version
AT17 Series
FPGA
Configuration
2
E
PROM
Description
The AT17C65/128/256 a nd AT17LV65 /128/256 (AT1 7 Series) FPGA Co nfiguratio n
EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17 Series is pack aged in the 8-pin
DIP and the popular 20-pin PLCC and SOIC. The AT17 Series family uses a simple
serial-access procedure to configure one or more FPGA devices. The AT17 Series
organization suppl ies enough me mory to config ure one or multipl e smaller FPG As.
Using a special feature of the AT17 Series, the user can select the polarity of the reset
function by programming a special EEPROM bit.
The AT17 Series can be programmed with industry standard programmers.
Pin Configurations
20-pin PLCC
20-Pin SOIC
65K, 128K and 256K
AT17C65
AT17C128
AT17C256
8-Pin DIP
0391E-A–5/97
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Controlling The AT17 Series Serial EEPROMs
Most connections between the FPGA device and the Serial
EEPROM are simple and self-explanatory.
• The DATA output of the AT17 Series drives DIN of the
FPGA devices.
• The master FPGA CCLK output drives the CLK input of
the AT17 Series.
•The CEO
input of the next AT17C/LV128/256 in a cascade chain of
PROMs.
•SER_EN
There are, however, two different ways to use the inputs
and OE, as shown in the AC Characteristi cs wave-
CE
forms.
output of any AT17C/LV128/256 drives the CE
must be connected to VCC.
Condition 1
The simplest connection is to have the FPGA D/P output
drive both CE
its simplicity, however, this method will fail if the FPGA
receives an ext ernal reset condition during the co nfigura-
and RESET/OE in para ll el (F i gure 1 ). Due to
tion cycle. If a system r eset is a pplied t o the FPG A, it wi ll
abort the original configuration and then reset itself for a
new configuration, as intended. Of course, the AT17 Series
does not see the external reset signal and will not reset its
internal address counters and, consequently, will remain
out of sync with the FPGA for the remainder of the configuration cycle.
Condition 2
The FPGA D/P output drives only the CE input of the AT17
Series, while its O E
input to the FPGA RESET
under all normal circumstances, even when the user aborts
a configuration before D/P
the RESET/OE
reset – clears the Configurator's internal address pointer,
so that the reconfigurati on starts at the b eginning. The
AT17 Series does n ot requir e an inverte r sinc e the RE SET
polarity is programmable.
input is driven by the inversion of the
input pin. This connection wor ks
has gone High. A High level on
input to the AT17C/LVxxx – du ring FPGA
Block Diagram
2
AT17 Series
AT17 Series
Pin Configurations
PLCC/
SOIC DIP
Pin Pin Name I/O Description
2 1 DATA I/O Three-state DATA output for reading. Input/Output pin for programming.
42CLK I
Clock input. Used to increment the internal address and bit counter for reading
and programming.
RESET/Output Enable input (when SER_EN is High). A Low level on both the
CE
and RESET/OE inputs enables the data output driver. A High level on
63RESET/OE
RESET/OE
input is programmable as eith er RESET/OE
describes the pin as RESET/OE
84CE
I Chip Enable input. Used for device selection. A Low level on both CE and OE
enables the data output driver. A High level on CE
and bit counters and forces te device into a low power mode. Note this pin will
not enable/disable the device in 2-wire Serial mode (ie; when SER_EN
10 5 GND Ground Pin
14 6 CEO
O Chip Enable Out output. This signal is asserted Low on the clock cycle following
the last bit read from the memory. It will stay Low as long as CE and OE
both Low. It will then follow CE
High until the entire PROM is read again and senses the status of RESET
polarity.
A2 I Device selection input, A2. This is used to enable (or select) the device during
programming and when SER_EN
details).
17 7 SER_EN
Serial enable is normally high during FPGA loading operations. Bringing
I
SER_EN low, enables the 2-wire serial interface for programming.
resets both the addresss and bit counters. A logic polarity of this
or RESET/OE. This document
.
disables both the address
is Low).
are
until OE goes High. Thereafter CEO will stay
is Low (see Programming Guide for more
20 8 V
CC
+3.3V/+5V power supply pin.
Absolute Maximum Ratings*
Operating Temperature.........................-55°C to +125°C
Storage Temperature............................-65°C to +150°C
Voltage on Any Pin
with Respect to Ground.................... -0.1V to V
Supply Voltage (Vcc).............................. -0.5 V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.)...260°C
ESD (R
= 1.5K, C
ZAP
= 100pF) ........................2000V
ZAP
CC +
0.5V
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the dev ice . This is a stress rating only an d
functional operati on of the de vi ce at these or an y
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or exten ded periods ma y affect d evice
reliability .
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