ATMEL ATV750BL-25SC, ATV750BL-25PI, ATV750BL-25PC, ATV750BL-25JI, ATV750BL-25JC Datasheet
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1
Features
•
Advanced, High-Speed Programmable Logic Device-Superset of 22V10
– Improved Performance - 7.5 ns tPD, 95 MHz External Operation
– Enhanced Logic Flexibility
– Backward Compatible with ATV750/L Software and Hardware
•
New Flip-Flop Features
– D- or T-Type
– Product Term or Direct Input Pin Clocking
•
High-Speed Erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-Pin Delay
•
Highest Density Programmable Logic Available in a 24-Pin Package
•
Increased Logic Flexibility
– 42 Array Inputs, 20 Sum Terms and 20 Flip-Flops
•
Enhanced Output Logic Flexibility
– All 20 Flip-Flops Feed Back Internally
– 10 Flip-Flops are Also Available as Outputs
•
Full Military, Commercial and Industrial Temperature Ranges
Logic Diagram
Description
The ATV750Bs are twice as powerful as most othe r 24-pin programmable logic
devices. Increased product terms, sum terms, flip-flops and output logic configurations
translate into mo re usable g ates. High-sp eed logic and unifor m, predict able delays
guarantee fast in-system performance.
Device ICC, Stand-By
ATV750B 125 mA
ATV750BL 15 mA
Rev. 0301D–05/98
High-Speed
UV-Erasable
Programmable
Logic Device
ATV750B
Pin Configurations
Pin Name Function
CLK Clock
IN Logic Inputs
I/O Bidirectional Buffers
* No Internal Connection
V
CC
+5V Supply
DIP/SOIC PLCC/LCC
T op View
(continued)
ATV750B
2
Each of the ATV750B’s 22 logic pi ns can be used as an
input. Ten of these can be used as inputs, outputs or bidirectional I/O pins. Each flip-flop is individually configurable as either D- or T-type. Each fl ip-flop output is fed
back into the array independently. This allows burying of all
the sum terms and flip-flops.
There are 171 total product terms avai lable. A va riable format is used to assign between four to eight product terms
per sum term. There are two sum terms per outpu t, providing added flexibility. Much more logic can be replaced by
this device than by any other 24-pin PLD. Wi th 20 sum
terms and flip-flops, complex state machines are easily
implemented with logic to spare.
Product terms provide individual clocks and asynchronous
resets for each flip-flop. Each flip-flop may also be individually configured to have direct input pin controlled clocking.
Each output has i ts o wn ena ble p roduct term. One produc t
term provides a com mon synchronous preset for a ll flipflops. Registe r prel oad fun ctions a re prov ided t o simp lify
testing. All registers automatically reset upon power up.
The ATV750BL is a low power device with speeds as fast
as 15 ns. The ATV750BL pro vides the optimu m low power
PLD solution, with full CMOS output levels. This device significantly reduces total system power, thereby allowing battery-powered operation.
Logic Options
Combinatorial Output Registered Output
Abosute Maximum Rating*
Temperature Under Bias................................ -55°C to +125°C
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the dev ice. Th is is a s tress rating only an d
functional oper ati on of the devi ce at t hes e o r any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect dev ice
reliability .
Note: 1. Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.Maximum output pin v ol tage is V
CC
+ 0.75V DC which
may o versh oot to +7.0V f or pulse s of less than 20
ns.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
Integrated UV Erase Dose ..............................7258 W•sec/cm
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Combined T erms Separate Terms
Combined T erms Separate Terms
ATV750B
3
Clock MUX
Output Options
Note: 1. See ordering information for valid speed and temperature combination.
DC and AC Operating Conditions
(1)
Commercial
-7, -10, -15
Commercial
-25 Industrial Military
Operating Temperature (Case) 0°C - 70°C 0°C - 70°C -40°C - 85°C -55°C - 125°C
V
CC
Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10%
SELECT
LOGIC
TO
CELL
CLOCK
PRODUCT
TERM
CLK
CKi
CKMUX
PIN
ATV750B
4
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Input Test Waveforms and
Measurement Levels
tR, tF < 3 ns (10% to 90%)
Output Test Load
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
LI
Input Load Current VIN = -0.1V to VCC + 1V 10 µA
I
LO
Output Leakage
Current
V
OUT
= -0.1V to VCC + 0.1V 10 µA
I
CC
Po wer Supply
Current, Standby
V
CC
= MAX,
V
IN
= MAX,
Outputs Open
B-7, -10
Com. 125 180 mA
Ind.,Mil. 125 190 mA
B-15, -25
Com. 125 180 mA
Ind.,Mil. 125 190 mA
BL-15
Com. 15 30 mA
Ind.,Mil. 15 30 mA
I
OS
(1)
Output Short
Circuit Current
V
OUT
= 0.5V -120 mA
V
IL
Input Low Voltage 4.5 ≤ VCC ≤ 5.5V -0.6 0.8 V
V
IH
Input High Voltage 2.0 V
CC
+ 0.75 V
V
OL
Output Low
Voltage
VIN = VIH or VIL,
V
CC
= MIN
I
OL
= 16 mA Com.,Ind. 0.5 V
I
OL
= 12 mA Mil. 0.5 V
I
OL
= 24 mA Com. 0.8 V
V
OH
Output High
Voltage
VIN = VIH or VIL,
V
CC
= MIN
IOH = -100 µAV
CC
- 0.3 V
I
OH
= -4.0 mA 2.4 V
ATV750B
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AC Wa veforms, Product Term Clock
(1)
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
Note: 1. See ordering information for valid par t numbers.
AC Characteristics, Product Term Clock
(1)
Symbol Parameter
-7 -10 B/BL-15 B/BL-25
UnitsMin Max Min Max Min Max Min Max
t
PD
Input or Feedback to
Non-Registered Outpu t
7.5 10 15 25 ns
t
EA
Input to Output Enable 7.5 10 15 25 ns
t
ER
Input to Output Disable 7.5 10 15 25 ns
t
CO
Clock to Output 3 7.5 4 10 5 12 6 20 ns
t
CF
Clock to Feedback 1 5 4 7.5 5 9 5 10 ns
t
S
Input Setup Time 3 4 8/12 14 ns
t
SF
Feedback Setup Time 3 4 7 7 ns
t
H
Hold Time 1 2 5/7 5/7 ns
t
P
Clock Period 7 11 14 17 ns
t
W
Clock Width 3.5 5.5 7 8.5 ns
F
MAX
External Feedback 1/(tS+tCO) 95 71 50/41 29 MHz
Internal Feedback 1/(t
SF+tCF
) 125 86 62 58 MHz
No Feedback 1/(t
P
) 142 90 71 58 MHz
t
AW
Asynchronous Reset Width 5 10 15 20 ns
t
AR
Asynchronous Reset
Recovery Time
31015 20ns
t
AP
Asynchronous Reset to
Registered Output Reset
812 1525ns
t
SP
Setup Time, Synchronous Preset 4 7 8 15 ns
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