ATI DDA124-BNC User Manual

Audio Technologies

Inc.

• Tel:

856-719-9900

• sales@atiaudio.com

•

www.

audio.com

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DDA & D

A S

AES/EBU DIGITAL

AUDIO

DISTRIBUTION

AMPLIFIERS

OPERATING AND MAINTENANCE MANUAL

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2008, Audio Technologies In

Audio Technologies

Inc.

• Tel:

856-719-9900

• sales@atiaudio.com

•

www.

audio.com

DESCRIPTION

The DDA Series of Digital Audio Distribution Amplifiers are designed to regenerate, isolate and distribute digital audio data formatted in accordance with specifications AES3-1992 and IEC 958. This is commonly called AES/EBU formatting.

The DSA Series operates much the same as the DDA Series; however, the DSA Series does not include the full featured display front panel and does not provide re-clocking of the digital input signal. The non-reclocking feature is essential when distributing Dolby E encoded AES signals and other clocked signals that should not be re-clocked.

DDAxxx-XLR and DSAxxx-XLR models use XLR connectors and operate from and drive a 110-ohm balanced shielded twisted pair distribution system per AES3-1992.

DDAxxx-BNC and DSAxxx-BNC models use BNC connectors and operate from and drive single-ended 75-ohm coaxial cable per AES-3id-1995 and are designed to integrate easily into video facilities.

S/PDIF (consumer) formatted digital audio data differs primarily in the use of consumer type "RCA" audio connectors in an unbalanced 75 ohm system and can be handled by a DDAxxx-BNC with use of an RCA to BNC input cable.

S/PDIF digital audio can be connected directly to a DSA106-RCA unit.

FEATURES

• Accepts sample rates from 27 to 96kHz

• Displays standard sample rates of 32, 44.1, 48, 88.2, 96 kHz (DDA only)

• Status and error LEDs show clock lock and data validity (DDA only)

• Adjustable input equalizers compensate for very long cable runs (DDA only)

• Data is relocked and regenerated before low-jitter transmission (DDA only)

• Loop thru transformer balanced and isolated inputs

• Switchable input termination resistors

• Individual, transformer balanced and isolated 110 ohm XLR outputs (-XLR only)

• Individual isolated 75-ohm BNC outputs (-BNC only)

• Single or dual inputs

• Up to 12 XLR or 24 BNC outputs

• Quiet, internal linear power supplies

• Attractive, 1RU package

Audio Technologies

Inc.

• Tel:

856-719-9900

• sales@atiaudio.com

•

www.

audio.com

DESCRIPTION

INPUTS

Incoming AES/EBU formatted digital audio data is applied to input transformers T8 (T9 for second input channel of dual unit). Both XLR and BNC inputs are balanced and DC isolated from ground. Input blocking capacitors C22 (C24) prevent accidental DC inputs from saturating (and perhaps damaging) the input transformers. Input termination resistors R25 (R26) at 75 ohms for BNC (and SP/DIF) inputs or 110 ohms for XLR inputs can be switched in or out of the circuit with rear panel DIP switches S1a (S1b). Inputs should always be terminated unless they are looped thru to another device or DDA input. The last device or input should always terminate the line.

INPUT EQUALIZERS

The input signals feed cable equalizer circuits U3 (U4) and associated components. Input equalization should only be necessary for extremely long input cable lengths and should only be used if proven to be necessary. The equalizers are adjustable with front panel multi-turn trimpots R63 (R66) so that only the minimum amount of boost required to compensate for excess cable rolloff can be added without over-equalization, which can degrade noise margins. See adjustment instructions in the INSTALLATION section. If input equalization is not required and you want to protect yourself from random control diddlers, you may disable the equalizers by removing jumpers E4 (E5).

RECEIVERS

(Note that DSA Series units do not re-clock and provide no front panel status information. The following section applies to DDA Series units only.)

The equalized AES/EBU data stream is applied to the receiver circuit U8 (U17) that is a Crystal Semiconductor CS8414 96kHz Digital Audio Receiver IC. The CS8414 receives the data, recovers the clock and synchronization signals and separates the audio and digital data. The audio data may be 16 to 24 bits at sample rates from 27 to 96 kHz.

Frame sync (FSYNC), Serial Clock (SCK), Serial audio data (SDATA), Channel status (C), User channel data (U), and data validity information (VERF) are passed directly to the transmitter IC for reformatting into the output data stream. VERF is an OR’ing of the validity information from the incoming data (V) with an internal error flag (ERF) that detects serious transmission errors such as parity errors, bi-phase coding violations and an out-of-lock PLL receiver. VERF then becomes the transmitted validity bit (V) and can be used by downstream error correction devices to interpolate through errors.

Received frequency information is encoded on U8 (U17) pins F0, F1 and F2 and is decoded by U14 (U19) into two BCD digits for display. Error information is encoded on pins E0, E1 and E2. It is decoded by 3 to 8 line decoder U20 (U22) and sent to the front panel display LEDs.

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